mirror of
https://github.com/RPCS3/rpcs3.git
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- Improved SPU Decoder.
This commit is contained in:
DH
parent
7e07cd9595
commit
991f281bbd
@ -1,6 +1,6 @@
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#pragma once
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#include "PPCInstrTable.h"
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#pragma warning( disable : 4800 )
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#pragma warning( disable : 4800 4554 )
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template<typename TO>
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class InstrCaller
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@ -481,22 +481,22 @@ static InstrList<count2, TO>* connect_list(InstrList<count1, TO>* parent, InstrL
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return child;
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}
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template<int count, typename TO>
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static InstrList<count, TO>* new_list(const CodeFieldBase& func, InstrCaller<TO>* error_func = nullptr)
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template<typename TO, uint from, uint to>
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static InstrList<1 << (to - from + 1), TO>* new_list(const CodeField<from, to>& func, InstrCaller<TO>* error_func = nullptr)
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{
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return new InstrList<count, TO>(func, error_func);
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return new InstrList<1 << (to - from + 1), TO>(func, error_func);
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}
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template<int count1, int count2, typename TO>
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static InstrList<count1, TO>* new_list(InstrList<count2, TO>* parent, int opcode, const CodeFieldBase& func, InstrCaller<TO>* error_func = nullptr)
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template<int count, typename TO, uint from, uint to>
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static InstrList<1 << (to - from + 1), TO>* new_list(InstrList<count, TO>* parent, int opcode, const CodeField<from, to>& func, InstrCaller<TO>* error_func = nullptr)
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{
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return connect_list(parent, new InstrList<count1, TO>(func, error_func), opcode);
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return connect_list(parent, new InstrList<1 << (to - from + 1), TO>(func, error_func), opcode);
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}
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template<int count1, int count2, typename TO>
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static InstrList<count1, TO>* new_list(InstrList<count2, TO>* parent, const CodeFieldBase& func, InstrCaller<TO>* error_func = nullptr)
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template<int count, typename TO, uint from, uint to>
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static InstrList<1 << (to - from + 1), TO>* new_list(InstrList<count, TO>* parent, const CodeField<from, to>& func, InstrCaller<TO>* error_func = nullptr)
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{
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return connect_list(parent, new InstrList<count1, TO>(func, error_func));
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return connect_list(parent, new InstrList<1 << (to - from + 1), TO>(func, error_func));
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}
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template<typename TO, int opcode, int count>
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@ -76,83 +76,83 @@ protected:
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return op;
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}
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void DisAsm_V4(const wxString& op, OP_REG v0, OP_REG v1, OP_REG v2, OP_REG v3)
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void DisAsm_V4(const wxString& op, u32 v0, u32 v1, u32 v2, u32 v3)
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{
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Write(wxString::Format("%s v%d,v%d,v%d,v%d", FixOp(op), v0, v1, v2, v3));
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}
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void DisAsm_V3_UIMM(const wxString& op, OP_REG v0, OP_REG v1, OP_REG v2, OP_uIMM uimm)
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void DisAsm_V3_UIMM(const wxString& op, u32 v0, u32 v1, u32 v2, u32 uimm)
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{
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Write(wxString::Format("%s v%d,v%d,v%d,%u #%x", FixOp(op), v0, v1, v2, uimm, uimm));
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}
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void DisAsm_V3(const wxString& op, OP_REG v0, OP_REG v1, OP_REG v2)
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void DisAsm_V3(const wxString& op, u32 v0, u32 v1, u32 v2)
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{
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Write(wxString::Format("%s v%d,v%d,v%d", FixOp(op), v0, v1, v2));
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}
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void DisAsm_V2_UIMM(const wxString& op, OP_REG v0, OP_REG v1, OP_uIMM uimm)
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void DisAsm_V2_UIMM(const wxString& op, u32 v0, u32 v1, u32 uimm)
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{
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Write(wxString::Format("%s v%d,v%d,%u #%x", FixOp(op), v0, v1, uimm, uimm));
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}
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void DisAsm_V2(const wxString& op, OP_REG v0, OP_REG v1)
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void DisAsm_V2(const wxString& op, u32 v0, u32 v1)
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{
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Write(wxString::Format("%s v%d,v%d", FixOp(op), v0, v1));
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}
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void DisAsm_V1_SIMM(const wxString& op, OP_REG v0, OP_sIMM simm)
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void DisAsm_V1_SIMM(const wxString& op, u32 v0, s32 simm)
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{
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Write(wxString::Format("%s v%d,%d #%x", FixOp(op), v0, simm, simm));
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}
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void DisAsm_V1(const wxString& op, OP_REG v0)
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void DisAsm_V1(const wxString& op, u32 v0)
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{
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Write(wxString::Format("%s v%d", FixOp(op), v0));
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}
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void DisAsm_V1_R2(const wxString& op, OP_REG v0, OP_REG r1, OP_REG r2)
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void DisAsm_V1_R2(const wxString& op, u32 v0, u32 r1, u32 r2)
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{
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Write(wxString::Format("%s v%d,r%d,r%d", FixOp(op), v0, r1, r2));
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}
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void DisAsm_CR1_F2_RC(const wxString& op, OP_REG cr0, OP_REG f0, OP_REG f1, bool rc)
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void DisAsm_CR1_F2_RC(const wxString& op, u32 cr0, u32 f0, u32 f1, bool rc)
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{
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Write(wxString::Format("%s%s cr%d,f%d,f%d", FixOp(op), rc ? "." : "", cr0, f0, f1));
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}
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void DisAsm_CR1_F2(const wxString& op, OP_REG cr0, OP_REG f0, OP_REG f1)
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void DisAsm_CR1_F2(const wxString& op, u32 cr0, u32 f0, u32 f1)
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{
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DisAsm_CR1_F2_RC(op, cr0, f0, f1, false);
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}
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void DisAsm_INT1_R2(const wxString& op, OP_REG i0, OP_REG r0, OP_REG r1)
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void DisAsm_INT1_R2(const wxString& op, u32 i0, u32 r0, u32 r1)
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{
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Write(wxString::Format("%s %d,r%d,r%d", FixOp(op), i0, r0, r1));
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}
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void DisAsm_INT1_R1_IMM(const wxString& op, OP_REG i0, OP_REG r0, OP_sIMM imm0)
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void DisAsm_INT1_R1_IMM(const wxString& op, u32 i0, u32 r0, s32 imm0)
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{
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Write(wxString::Format("%s %d,r%d,%d #%x", FixOp(op), i0, r0, imm0, imm0));
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}
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void DisAsm_INT1_R1_RC(const wxString& op, OP_REG i0, OP_REG r0, bool rc)
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void DisAsm_INT1_R1_RC(const wxString& op, u32 i0, u32 r0, bool rc)
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{
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Write(wxString::Format("%s%s %d,r%d", FixOp(op), rc ? "." : "", i0, r0));
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}
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void DisAsm_INT1_R1(const wxString& op, OP_REG i0, OP_REG r0)
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void DisAsm_INT1_R1(const wxString& op, u32 i0, u32 r0)
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{
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DisAsm_INT1_R1_RC(op, i0, r0, false);
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}
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void DisAsm_F4_RC(const wxString& op, OP_REG f0, OP_REG f1, OP_REG f2, OP_REG f3, bool rc)
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void DisAsm_F4_RC(const wxString& op, u32 f0, u32 f1, u32 f2, u32 f3, bool rc)
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{
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Write(wxString::Format("%s%s f%d,f%d,f%d,f%d", FixOp(op), rc ? "." : "", f0, f1, f2, f3));
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}
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void DisAsm_F3_RC(const wxString& op, OP_REG f0, OP_REG f1, OP_REG f2, bool rc)
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void DisAsm_F3_RC(const wxString& op, u32 f0, u32 f1, u32 f2, bool rc)
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{
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Write(wxString::Format("%s%s f%d,f%d,f%d", FixOp(op), rc ? "." : "", f0, f1, f2));
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}
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void DisAsm_F3(const wxString& op, OP_REG f0, OP_REG f1, OP_REG f2)
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void DisAsm_F3(const wxString& op, u32 f0, u32 f1, u32 f2)
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{
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DisAsm_F3_RC(op, f0, f1, f2, false);
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}
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void DisAsm_F2_RC(const wxString& op, OP_REG f0, OP_REG f1, bool rc)
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void DisAsm_F2_RC(const wxString& op, u32 f0, u32 f1, bool rc)
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{
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Write(wxString::Format("%s%s f%d,f%d", FixOp(op), rc ? "." : "", f0, f1));
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}
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void DisAsm_F2(const wxString& op, OP_REG f0, OP_REG f1)
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void DisAsm_F2(const wxString& op, u32 f0, u32 f1)
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{
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DisAsm_F2_RC(op, f0, f1, false);
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}
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void DisAsm_F1_R2(const wxString& op, OP_REG f0, OP_REG r0, OP_REG r1)
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void DisAsm_F1_R2(const wxString& op, u32 f0, u32 r0, u32 r1)
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{
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if(m_mode == CompilerElfMode)
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{
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@ -162,7 +162,7 @@ protected:
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Write(wxString::Format("%s f%d,r%d(r%d)", FixOp(op), f0, r0, r1));
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}
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void DisAsm_F1_IMM_R1_RC(const wxString& op, OP_REG f0, OP_sIMM imm0, OP_REG r0, bool rc)
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void DisAsm_F1_IMM_R1_RC(const wxString& op, u32 f0, s32 imm0, u32 r0, bool rc)
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{
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if(m_mode == CompilerElfMode)
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{
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@ -172,75 +172,75 @@ protected:
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Write(wxString::Format("%s%s f%d,%d(r%d) #%x", FixOp(op), rc ? "." : "", f0, imm0, r0, imm0));
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}
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void DisAsm_F1_IMM_R1(const wxString& op, OP_REG f0, OP_sIMM imm0, OP_REG r0)
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void DisAsm_F1_IMM_R1(const wxString& op, u32 f0, s32 imm0, u32 r0)
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{
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DisAsm_F1_IMM_R1_RC(op, f0, imm0, r0, false);
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}
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void DisAsm_F1_RC(const wxString& op, OP_REG f0, bool rc)
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void DisAsm_F1_RC(const wxString& op, u32 f0, bool rc)
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{
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Write(wxString::Format("%s%s f%d", FixOp(op), rc ? "." : "", f0));
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}
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void DisAsm_R1_RC(const wxString& op, OP_REG r0, bool rc)
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void DisAsm_R1_RC(const wxString& op, u32 r0, bool rc)
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{
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Write(wxString::Format("%s%s r%d", FixOp(op), rc ? "." : "", r0));
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}
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void DisAsm_R1(const wxString& op, OP_REG r0)
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void DisAsm_R1(const wxString& op, u32 r0)
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{
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DisAsm_R1_RC(op, r0, false);
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}
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void DisAsm_R2_OE_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG oe, bool rc)
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void DisAsm_R2_OE_RC(const wxString& op, u32 r0, u32 r1, u32 oe, bool rc)
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{
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Write(wxString::Format("%s%s%s r%d,r%d", FixOp(op), oe ? "o" : "", rc ? "." : "", r0, r1));
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}
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void DisAsm_R2_RC(const wxString& op, OP_REG r0, OP_REG r1, bool rc)
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void DisAsm_R2_RC(const wxString& op, u32 r0, u32 r1, bool rc)
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{
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DisAsm_R2_OE_RC(op, r0, r1, false, rc);
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}
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void DisAsm_R2(const wxString& op, OP_REG r0, OP_REG r1)
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void DisAsm_R2(const wxString& op, u32 r0, u32 r1)
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{
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DisAsm_R2_RC(op, r0, r1, false);
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}
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void DisAsm_R3_OE_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2, OP_REG oe, bool rc)
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void DisAsm_R3_OE_RC(const wxString& op, u32 r0, u32 r1, u32 r2, u32 oe, bool rc)
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{
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Write(wxString::Format("%s%s%s r%d,r%d,r%d", FixOp(op), oe ? "o" : "", rc ? "." : "", r0, r1, r2));
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}
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void DisAsm_R3_INT2_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2, OP_sIMM i0, OP_sIMM i1, bool rc)
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void DisAsm_R3_INT2_RC(const wxString& op, u32 r0, u32 r1, u32 r2, s32 i0, s32 i1, bool rc)
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{
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Write(wxString::Format("%s%s r%d,r%d,r%d,%d,%d", FixOp(op), rc ? "." : "", r0, r1, r2, i0, i1));
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}
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void DisAsm_R3_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2, bool rc)
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void DisAsm_R3_RC(const wxString& op, u32 r0, u32 r1, u32 r2, bool rc)
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{
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DisAsm_R3_OE_RC(op, r0, r1, r2, false, rc);
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}
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void DisAsm_R3(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2)
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void DisAsm_R3(const wxString& op, u32 r0, u32 r1, u32 r2)
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{
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DisAsm_R3_RC(op, r0, r1, r2, false);
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}
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void DisAsm_R2_INT3_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1, OP_sIMM i2, bool rc)
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void DisAsm_R2_INT3_RC(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2, bool rc)
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{
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Write(wxString::Format("%s%s r%d,r%d,%d,%d,%d", FixOp(op), rc ? "." : "", r0, r1, i0, i1, i2));
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}
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void DisAsm_R2_INT3(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1, OP_sIMM i2)
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void DisAsm_R2_INT3(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2)
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{
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DisAsm_R2_INT3_RC(op, r0, r1, i0, i1, i2, false);
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}
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void DisAsm_R2_INT2_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1, bool rc)
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void DisAsm_R2_INT2_RC(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1, bool rc)
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{
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Write(wxString::Format("%s%s r%d,r%d,%d,%d", FixOp(op), rc ? "." : "", r0, r1, i0, i1));
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}
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void DisAsm_R2_INT2(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1)
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void DisAsm_R2_INT2(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1)
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{
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DisAsm_R2_INT2_RC(op, r0, r1, i0, i1, false);
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}
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void DisAsm_R2_INT1_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, bool rc)
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void DisAsm_R2_INT1_RC(const wxString& op, u32 r0, u32 r1, s32 i0, bool rc)
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{
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Write(wxString::Format("%s%s r%d,r%d,%d", FixOp(op), rc ? "." : "", r0, r1, i0));
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}
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void DisAsm_R2_INT1(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0)
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void DisAsm_R2_INT1(const wxString& op, u32 r0, u32 r1, s32 i0)
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{
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DisAsm_R2_INT1_RC(op, r0, r1, i0, false);
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}
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void DisAsm_R2_IMM(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM imm0)
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void DisAsm_R2_IMM(const wxString& op, u32 r0, u32 r1, s32 imm0)
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{
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if(m_mode == CompilerElfMode)
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{
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@ -250,27 +250,27 @@ protected:
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Write(wxString::Format("%s r%d,%d(r%d) #%x", FixOp(op), r0, imm0, r1, imm0));
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}
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void DisAsm_R1_IMM(const wxString& op, OP_REG r0, OP_sIMM imm0)
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void DisAsm_R1_IMM(const wxString& op, u32 r0, s32 imm0)
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{
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Write(wxString::Format("%s r%d,%d #%x", FixOp(op), r0, imm0, imm0));
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}
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void DisAsm_IMM_R1(const wxString& op, OP_sIMM imm0, OP_REG r0)
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void DisAsm_IMM_R1(const wxString& op, s32 imm0, u32 r0)
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{
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Write(wxString::Format("%s %d,r%d #%x", FixOp(op), imm0, r0, imm0));
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}
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void DisAsm_CR1_R1_IMM(const wxString& op, OP_REG cr0, OP_REG r0, OP_sIMM imm0)
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void DisAsm_CR1_R1_IMM(const wxString& op, u32 cr0, u32 r0, s32 imm0)
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{
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Write(wxString::Format("%s cr%d,r%d,%d #%x", FixOp(op), cr0, r0, imm0, imm0));
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}
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void DisAsm_CR1_R2_RC(const wxString& op, OP_REG cr0, OP_REG r0, OP_REG r1, bool rc)
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void DisAsm_CR1_R2_RC(const wxString& op, u32 cr0, u32 r0, u32 r1, bool rc)
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{
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Write(wxString::Format("%s%s cr%d,r%d,r%d", FixOp(op), rc ? "." : "", cr0, r0, r1));
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}
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void DisAsm_CR1_R2(const wxString& op, OP_REG cr0, OP_REG r0, OP_REG r1)
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void DisAsm_CR1_R2(const wxString& op, u32 cr0, u32 r0, u32 r1)
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{
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DisAsm_CR1_R2_RC(op, cr0, r0, r1, false);
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}
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void DisAsm_CR2(const wxString& op, OP_REG cr0, OP_REG cr1)
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void DisAsm_CR2(const wxString& op, u32 cr0, u32 cr1)
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{
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Write(wxString::Format("%s cr%d,cr%d", FixOp(op), cr0, cr1));
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}
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@ -290,11 +290,11 @@ protected:
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{
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Write(wxString::Format("%s 0x%x", FixOp(op), pc));
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}
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void DisAsm_B2_BRANCH(const wxString& op, OP_REG b0, OP_REG b1, const int pc)
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void DisAsm_B2_BRANCH(const wxString& op, u32 b0, u32 b1, const int pc)
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{
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Write(wxString::Format("%s %d,%d,0x%x ", FixOp(op), b0, b1, DisAsmBranchTarget(pc)));
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}
|
||||
void DisAsm_CR_BRANCH(const wxString& op, OP_REG cr, const int pc)
|
||||
void DisAsm_CR_BRANCH(const wxString& op, u32 cr, const int pc)
|
||||
{
|
||||
Write(wxString::Format("%s cr%d,0x%x ", FixOp(op), cr, DisAsmBranchTarget(pc)));
|
||||
}
|
||||
|
||||
@ -77,6 +77,8 @@ public:
|
||||
}
|
||||
};
|
||||
|
||||
static CodeField<0, 31> GetCode;
|
||||
|
||||
template<uint from1, uint to1, uint from2, uint to2 = from2, uint offset = 0>
|
||||
class DoubleCodeField : public CodeField<from1, to1>
|
||||
{
|
||||
@ -133,3 +135,68 @@ public:
|
||||
return decode(data);
|
||||
}
|
||||
};
|
||||
|
||||
template<uint from, uint to = from, uint _offset = 0>
|
||||
class CodeFieldOffset : public CodeField<from, to>
|
||||
{
|
||||
static const int offset = _offset;
|
||||
|
||||
public:
|
||||
CodeFieldOffset(CodeFieldType type = FIELD_IMM) : CodeField(type)
|
||||
{
|
||||
}
|
||||
|
||||
static __forceinline u32 decode(u32 data)
|
||||
{
|
||||
return ((data & mask) >> shift) << offset;
|
||||
}
|
||||
|
||||
static __forceinline void encode(u32& data, u32 value)
|
||||
{
|
||||
data &= ~mask;
|
||||
data |= ((value >> offset) << shift) & mask;
|
||||
}
|
||||
|
||||
virtual u32 operator ()(u32 data) const
|
||||
{
|
||||
return decode(data);
|
||||
}
|
||||
|
||||
virtual void operator ()(u32& data, u32 value) const
|
||||
{
|
||||
return encode(data, value);
|
||||
}
|
||||
};
|
||||
|
||||
template<uint from, uint to = from, uint _offset = 0, uint size = to - from + 1>
|
||||
class CodeFieldSignedOffset : public CodeFieldSigned<from, to, size>
|
||||
{
|
||||
static const int offset = _offset;
|
||||
|
||||
public:
|
||||
CodeFieldSignedOffset(CodeFieldType type = FIELD_IMM) : CodeFieldSigned(type)
|
||||
{
|
||||
}
|
||||
|
||||
static __forceinline u32 decode(u32 data)
|
||||
{
|
||||
return sign<size>((data & mask) >> shift) << offset;
|
||||
}
|
||||
|
||||
static __forceinline void encode(u32& data, u32 value)
|
||||
{
|
||||
data &= ~mask;
|
||||
data |= ((value >> offset) << shift) & mask;
|
||||
}
|
||||
|
||||
virtual u32 operator ()(u32 data) const
|
||||
{
|
||||
return decode(data);
|
||||
}
|
||||
|
||||
virtual void operator ()(u32& data, u32 value) const
|
||||
{
|
||||
return encode(data, value);
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -240,20 +240,19 @@ namespace PPU_instr
|
||||
static CodeField<26, 30> GD_3f;//0x1f
|
||||
static CodeField<21, 30> GD_3f_0; //0x3ff
|
||||
|
||||
static CodeField<0, 31> GetCode;
|
||||
static CodeField<9, 10> STRM;
|
||||
|
||||
static auto main_list = new_list<0x40>(OPCD, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, OPCD));
|
||||
static auto g04_list = new_list<0x40>(main_list, PPU_opcodes::G_04, GD_04);
|
||||
static auto g04_0_list = new_list<0x800>(g04_list, GD_04_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_04_0));
|
||||
static auto g13_list = new_list<0x400>(main_list, PPU_opcodes::G_13, GD_13, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_13));
|
||||
static auto g1e_list = new_list<0x4>(main_list, PPU_opcodes::G_1e, GD_1e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1e));
|
||||
static auto g1f_list = new_list<0x400>(main_list, PPU_opcodes::G_1f, GD_1f, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1f));
|
||||
static auto g3a_list = new_list<0x4>(main_list, PPU_opcodes::G_3a, GD_3a, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3a));
|
||||
static auto g3b_list = new_list<0x20>(main_list, PPU_opcodes::G_3b, GD_3b, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3b));
|
||||
static auto g3e_list = new_list<0x4>(main_list, PPU_opcodes::G_3e, GD_3e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3e));
|
||||
static auto g3f_list = new_list<0x20>(main_list, PPU_opcodes::G_3f, GD_3f);
|
||||
static auto g3f_0_list = new_list<0x400>(g3f_list, GD_3f_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3f_0));
|
||||
static auto main_list = new_list(OPCD, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, OPCD));
|
||||
static auto g04_list = new_list(main_list, PPU_opcodes::G_04, GD_04);
|
||||
static auto g04_0_list = new_list(g04_list, GD_04_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_04_0));
|
||||
static auto g13_list = new_list(main_list, PPU_opcodes::G_13, GD_13, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_13));
|
||||
static auto g1e_list = new_list(main_list, PPU_opcodes::G_1e, GD_1e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1e));
|
||||
static auto g1f_list = new_list(main_list, PPU_opcodes::G_1f, GD_1f, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1f));
|
||||
static auto g3a_list = new_list(main_list, PPU_opcodes::G_3a, GD_3a, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3a));
|
||||
static auto g3b_list = new_list(main_list, PPU_opcodes::G_3b, GD_3b, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3b));
|
||||
static auto g3e_list = new_list(main_list, PPU_opcodes::G_3e, GD_3e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3e));
|
||||
static auto g3f_list = new_list(main_list, PPU_opcodes::G_3f, GD_3f);
|
||||
static auto g3f_0_list = new_list(g3f_list, GD_3f_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3f_0));
|
||||
|
||||
#define bind_instr(list, name, ...) \
|
||||
static const auto& name = make_instr<PPU_opcodes::name>(list, #name, &PPU_Opcodes::name, ##__VA_ARGS__)
|
||||
@ -637,4 +636,6 @@ namespace PPU_instr
|
||||
bind_instr(g3f_0_list, MTFSFI, CRFD, I, RC);
|
||||
bind_instr(g3f_0_list, MFFS, FRD, RC);
|
||||
bind_instr(g3f_0_list, MTFSF, FLM, FRB, RC);
|
||||
|
||||
#undef bind_instr
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,13 +1,5 @@
|
||||
#pragma once
|
||||
|
||||
#define OP_REG u32
|
||||
#define OP_sIMM s32
|
||||
#define OP_uIMM u32
|
||||
#define START_OPCODES_GROUP(x) /*x*/
|
||||
#define ADD_OPCODE(name, regs) virtual void(##name##)##regs##=0
|
||||
#define ADD_NULL_OPCODE(name) virtual void(##name##)()=0
|
||||
#define END_OPCODES_GROUP(x) /*x*/
|
||||
|
||||
namespace PPU_opcodes
|
||||
{
|
||||
enum PPU_MainOpcodes
|
||||
@ -447,415 +439,382 @@ public:
|
||||
return pc + (imm & ~0x3);
|
||||
}
|
||||
|
||||
ADD_NULL_OPCODE(NULL_OP);
|
||||
ADD_NULL_OPCODE(NOP);
|
||||
virtual void NULL_OP() = 0;
|
||||
virtual void NOP() = 0;
|
||||
|
||||
ADD_OPCODE(TDI,(OP_uIMM to, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(TWI,(OP_uIMM to, OP_REG ra, OP_sIMM simm16));
|
||||
virtual void TDI(u32 to, u32 ra, s32 simm16) = 0;
|
||||
virtual void TWI(u32 to, u32 ra, s32 simm16) = 0;
|
||||
|
||||
START_OPCODES_GROUP(G_04)
|
||||
ADD_OPCODE(MFVSCR,(OP_REG vd));
|
||||
ADD_OPCODE(MTVSCR,(OP_REG vb));
|
||||
ADD_OPCODE(VADDCUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDSBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDSHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDSWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDUBM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDUBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDUHM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDUHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDUWM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VADDUWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAND,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VANDC,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAVGSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAVGSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAVGSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAVGUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAVGUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VAVGUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCFSX,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VCFUX,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VCMPBFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPBFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQUB_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQUH_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPEQUW_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGEFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGEFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTFP_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTSB_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTSH_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTSW_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTUB_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTUH_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCMPGTUW_,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VCTSXS,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VCTUXS,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VEXPTEFP,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VLOGEFP,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VMADDFP,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMAXFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMAXSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMAXSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMAXSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMAXUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMAXUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMAXUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMHADDSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMHRADDSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMINFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMINSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMINSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMINSW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMINUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMINUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMINUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMLADDUHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMRGHB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMRGHH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMRGHW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMRGLB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMRGLH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMRGLW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMSUMMBM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMSUMSHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMSUMSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMSUMUBM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMSUMUHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMSUMUHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VMULESB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULESH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULEUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULEUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULOSB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULOSH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULOUB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VMULOUH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VNMSUBFP,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VNOR,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VOR,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPERM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VPKPX,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKSHSS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKSHUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKSWSS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKSWUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKUHUM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKUHUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKUWUM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VPKUWUS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VREFP,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VRFIM,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VRFIN,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VRFIP,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VRFIZ,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VRLB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VRLH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VRLW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VRSQRTEFP,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VSEL,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc));
|
||||
ADD_OPCODE(VSL,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSLB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSLDOI,(OP_REG vd, OP_REG va, OP_REG vb, OP_uIMM sh));
|
||||
ADD_OPCODE(VSLH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSLO,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSLW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSPLTB,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VSPLTH,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VSPLTISB,(OP_REG vd, OP_sIMM simm5));
|
||||
ADD_OPCODE(VSPLTISH,(OP_REG vd, OP_sIMM simm5));
|
||||
ADD_OPCODE(VSPLTISW,(OP_REG vd, OP_sIMM simm5));
|
||||
ADD_OPCODE(VSPLTW,(OP_REG vd, OP_uIMM uimm5, OP_REG vb));
|
||||
ADD_OPCODE(VSR,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRAB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRAH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRAW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRB,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRH,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRO,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSRW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBCUW,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBFP,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBSBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBSHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBSWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBUBM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBUBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBUHM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBUHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBUWM,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUBUWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUMSWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUM2SWS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUM4SBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUM4SHS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VSUM4UBS,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
ADD_OPCODE(VUPKHPX,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VUPKHSB,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VUPKHSH,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VUPKLPX,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VUPKLSB,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VUPKLSH,(OP_REG vd, OP_REG vb));
|
||||
ADD_OPCODE(VXOR,(OP_REG vd, OP_REG va, OP_REG vb));
|
||||
END_OPCODES_GROUP(G_04);
|
||||
virtual void MFVSCR(u32 vd) = 0;
|
||||
virtual void MTVSCR(u32 vb) = 0;
|
||||
virtual void VADDCUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDSBS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDSHS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDSWS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDUBM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDUBS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDUHM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDUHS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDUWM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VADDUWS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAND(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VANDC(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAVGSB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAVGSH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAVGSW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAVGUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAVGUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VAVGUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCFSX(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VCFUX(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VCMPBFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPBFP_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQFP_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQUB_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQUH_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPEQUW_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGEFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGEFP_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTFP_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTSB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTSB_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTSH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTSH_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTSW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTSW_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTUB_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTUH_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCMPGTUW_(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VCTSXS(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VCTUXS(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VEXPTEFP(u32 vd, u32 vb) = 0;
|
||||
virtual void VLOGEFP(u32 vd, u32 vb) = 0;
|
||||
virtual void VMADDFP(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMAXFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMAXSB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMAXSH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMAXSW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMAXUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMAXUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMAXUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMINFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMINSB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMINSH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMINSW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMINUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMINUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMINUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMRGHB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMRGHH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMRGHW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMRGLB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMRGLH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMRGLW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMSUMMBM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMSUMSHM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMSUMSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMSUMUBM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMSUMUHM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMSUMUHS(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VMULESB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULESH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULEUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULEUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULOSB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULOSH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULOUB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VMULOUH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VNMSUBFP(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VNOR(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VOR(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPERM(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VPKPX(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKSHSS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKSHUS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKSWSS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKSWUS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKUHUM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKUHUS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKUWUM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VPKUWUS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VREFP(u32 vd, u32 vb) = 0;
|
||||
virtual void VRFIM(u32 vd, u32 vb) = 0;
|
||||
virtual void VRFIN(u32 vd, u32 vb) = 0;
|
||||
virtual void VRFIP(u32 vd, u32 vb) = 0;
|
||||
virtual void VRFIZ(u32 vd, u32 vb) = 0;
|
||||
virtual void VRLB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VRLH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VRLW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VRSQRTEFP(u32 vd, u32 vb) = 0;
|
||||
virtual void VSEL(u32 vd, u32 va, u32 vb, u32 vc) = 0;
|
||||
virtual void VSL(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSLB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSLDOI(u32 vd, u32 va, u32 vb, u32 sh) = 0;
|
||||
virtual void VSLH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSLO(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSLW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSPLTB(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VSPLTH(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VSPLTISB(u32 vd, s32 simm5) = 0;
|
||||
virtual void VSPLTISH(u32 vd, s32 simm5) = 0;
|
||||
virtual void VSPLTISW(u32 vd, s32 simm5) = 0;
|
||||
virtual void VSPLTW(u32 vd, u32 uimm5, u32 vb) = 0;
|
||||
virtual void VSR(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRAB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRAH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRAW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRB(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRH(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRO(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSRW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBCUW(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBFP(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBSBS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBSHS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBSWS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBUBM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBUBS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBUHM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBUHS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBUWM(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUBUWS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUMSWS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUM2SWS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUM4SBS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUM4SHS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VSUM4UBS(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void VUPKHPX(u32 vd, u32 vb) = 0;
|
||||
virtual void VUPKHSB(u32 vd, u32 vb) = 0;
|
||||
virtual void VUPKHSH(u32 vd, u32 vb) = 0;
|
||||
virtual void VUPKLPX(u32 vd, u32 vb) = 0;
|
||||
virtual void VUPKLSB(u32 vd, u32 vb) = 0;
|
||||
virtual void VUPKLSH(u32 vd, u32 vb) = 0;
|
||||
virtual void VXOR(u32 vd, u32 va, u32 vb) = 0;
|
||||
virtual void MULLI(u32 rd, u32 ra, s32 simm16) = 0;
|
||||
virtual void SUBFIC(u32 rd, u32 ra, s32 simm16) = 0;
|
||||
virtual void CMPLI(u32 bf, u32 l, u32 ra, u32 uimm16) = 0;
|
||||
virtual void CMPI(u32 bf, u32 l, u32 ra, s32 simm16) = 0;
|
||||
virtual void ADDIC(u32 rd, u32 ra, s32 simm16) = 0;
|
||||
virtual void ADDIC_(u32 rd, u32 ra, s32 simm16) = 0;
|
||||
virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0;
|
||||
virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0;
|
||||
virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0;
|
||||
virtual void SC(s32 sc_code) = 0;
|
||||
virtual void B(s32 ll, u32 aa, u32 lk) = 0;
|
||||
virtual void MCRF(u32 crfd, u32 crfs) = 0;
|
||||
virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
|
||||
virtual void CRNOR(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void CRANDC(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void ISYNC() = 0;
|
||||
virtual void CRXOR(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void CRNAND(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void CRAND(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void CREQV(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void CRORC(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void CROR(u32 bt, u32 ba, u32 bb) = 0;
|
||||
virtual void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
|
||||
virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0;
|
||||
virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0;
|
||||
virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) = 0;
|
||||
virtual void ORI(u32 rs, u32 ra, u32 uimm16) = 0;
|
||||
virtual void ORIS(u32 rs, u32 ra, u32 uimm16) = 0;
|
||||
virtual void XORI(u32 ra, u32 rs, u32 uimm16) = 0;
|
||||
virtual void XORIS(u32 ra, u32 rs, u32 uimm16) = 0;
|
||||
virtual void ANDI_(u32 ra, u32 rs, u32 uimm16) = 0;
|
||||
virtual void ANDIS_(u32 ra, u32 rs, u32 uimm16) = 0;
|
||||
virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0;
|
||||
virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) = 0;
|
||||
virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0;
|
||||
virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0;
|
||||
virtual void CMP(u32 crfd, u32 l, u32 ra, u32 rb) = 0;
|
||||
virtual void TW(u32 to, u32 ra, u32 rb) = 0;
|
||||
virtual void LVSL(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void LVEBX(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
||||
virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
||||
virtual void MFOCRF(u32 a, u32 rd, u32 crm) = 0;
|
||||
virtual void LWARX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void LDX(u32 ra, u32 rs, u32 rb) = 0;
|
||||
virtual void LWZX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void SLW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void CNTLZW(u32 ra, u32 rs, bool rc) = 0;
|
||||
virtual void SLD(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void AND(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void CMPL(u32 bf, u32 l, u32 ra, u32 rb) = 0;
|
||||
virtual void LVSR(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void LVEHX(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void LDUX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void DCBST(u32 ra, u32 rb) = 0;
|
||||
virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0;
|
||||
virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
||||
virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0;
|
||||
virtual void LDARX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void DCBF(u32 ra, u32 rb) = 0;
|
||||
virtual void LBZX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void LVX(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void NEG(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
||||
virtual void LBZUX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void NOR(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void STVEBX(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void MTOCRF(u32 crm, u32 rs) = 0;
|
||||
virtual void STDX(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void STWCX_(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void STWX(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void STVEHX(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void STDUX(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void STVEWX(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
||||
virtual void STDCX_(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void STBX(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void STVX(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
||||
virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void DCBTST(u32 th, u32 ra, u32 rb) = 0;
|
||||
virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void DCBT(u32 ra, u32 rb, u32 th) = 0;
|
||||
virtual void LHZX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void EQV(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void ECIWX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void LHZUX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void XOR(u32 rs, u32 ra, u32 rb, bool rc) = 0;
|
||||
virtual void MFSPR(u32 rd, u32 spr) = 0;
|
||||
virtual void DST(u32 ra, u32 rb, u32 strm, u32 t) = 0;
|
||||
virtual void LHAX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void LVXL(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void ABS(u32 rd, u32 ra, u32 oe, bool rc) = 0;
|
||||
virtual void MFTB(u32 rd, u32 spr) = 0;
|
||||
virtual void DSTST(u32 ra, u32 rb, u32 strm, u32 t) = 0;
|
||||
virtual void LHAUX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void STHX(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void ORC(u32 rs, u32 ra, u32 rb, bool rc) = 0;
|
||||
virtual void ECOWX(u32 rs, u32 ra, u32 rb) = 0;
|
||||
virtual void OR(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void MTSPR(u32 spr, u32 rs) = 0;
|
||||
//DCBI
|
||||
virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
|
||||
virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0;
|
||||
virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void SRD(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void LVRX(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void LFSUX(u32 frd, u32 ra, u32 rb) = 0;
|
||||
virtual void SYNC(u32 l) = 0;
|
||||
virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0;
|
||||
virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0;
|
||||
virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
|
||||
virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;
|
||||
virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0;
|
||||
virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0;
|
||||
virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void SRAD(u32 ra, u32 rs, u32 rb, bool rc) = 0;
|
||||
virtual void LVRXL(u32 vd, u32 ra, u32 rb) = 0;
|
||||
virtual void DSS(u32 strm, u32 a) = 0;
|
||||
virtual void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) = 0;
|
||||
virtual void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) = 0;
|
||||
virtual void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) = 0;
|
||||
virtual void EIEIO() = 0;
|
||||
virtual void STVLXL(u32 sd, u32 ra, u32 rb) = 0;
|
||||
virtual void EXTSH(u32 ra, u32 rs, bool rc) = 0;
|
||||
virtual void STVRXL(u32 sd, u32 ra, u32 rb) = 0;
|
||||
virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0;
|
||||
virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0;
|
||||
virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0;
|
||||
//ICBI
|
||||
virtual void DCBZ(u32 ra, u32 rb) = 0;
|
||||
virtual void LWZ(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void LWZU(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void LBZ(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void LBZU(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void STW(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void STWU(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void STB(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void STBU(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void LHZ(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void LHZU(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void STH(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void STHU(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void LMW(u32 rd, u32 ra, s32 d) = 0;
|
||||
virtual void STMW(u32 rs, u32 ra, s32 d) = 0;
|
||||
virtual void LFS(u32 frd, u32 ra, s32 d) = 0;
|
||||
virtual void LFSU(u32 frd, u32 ra, s32 d) = 0;
|
||||
virtual void LFD(u32 frd, u32 ra, s32 d) = 0;
|
||||
virtual void LFDU(u32 frd, u32 ra, s32 d) = 0;
|
||||
virtual void STFS(u32 frs, u32 ra, s32 d) = 0;
|
||||
virtual void STFSU(u32 frs, u32 ra, s32 d) = 0;
|
||||
virtual void STFD(u32 frs, u32 ra, s32 d) = 0;
|
||||
virtual void STFDU(u32 frs, u32 ra, s32 d) = 0;
|
||||
virtual void LD(u32 rd, u32 ra, s32 ds) = 0;
|
||||
virtual void LDU(u32 rd, u32 ra, s32 ds) = 0;
|
||||
virtual void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) = 0;
|
||||
virtual void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) = 0;
|
||||
virtual void FADDS(u32 frd, u32 fra, u32 frb, bool rc) = 0;
|
||||
virtual void FSQRTS(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FRES(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FMULS(u32 frd, u32 fra, u32 frc, bool rc) = 0;
|
||||
virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void STD(u32 rs, u32 ra, s32 ds) = 0;
|
||||
virtual void STDU(u32 rs, u32 ra, s32 ds) = 0;
|
||||
virtual void MTFSB1(u32 bt, bool rc) = 0;
|
||||
virtual void MCRFS(u32 bf, u32 bfa) = 0;
|
||||
virtual void MTFSB0(u32 bt, bool rc) = 0;
|
||||
virtual void MTFSFI(u32 crfd, u32 i, bool rc) = 0;
|
||||
virtual void MFFS(u32 frd, bool rc) = 0;
|
||||
virtual void MTFSF(u32 flm, u32 frb, bool rc) = 0;
|
||||
|
||||
ADD_OPCODE(MULLI,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(SUBFIC,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(CMPLI,(OP_REG bf, OP_REG l, OP_REG ra, OP_uIMM uimm16));
|
||||
ADD_OPCODE(CMPI,(OP_REG bf, OP_REG l, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(ADDIC,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(ADDIC_,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(ADDI,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(ADDIS,(OP_REG rd, OP_REG ra, OP_sIMM simm16));
|
||||
ADD_OPCODE(BC,(OP_REG bo, OP_REG bi, OP_sIMM bd, OP_REG aa, OP_REG lk));
|
||||
ADD_OPCODE(SC,(OP_sIMM sc_code));
|
||||
ADD_OPCODE(B,(OP_sIMM ll, OP_REG aa, OP_REG lk));
|
||||
|
||||
START_OPCODES_GROUP(G_13)
|
||||
ADD_OPCODE(MCRF,(OP_REG crfd, OP_REG crfs));
|
||||
ADD_OPCODE(BCLR,(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk));
|
||||
ADD_OPCODE(CRNOR,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(CRANDC,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(ISYNC,());
|
||||
ADD_OPCODE(CRXOR,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(CRNAND,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(CRAND,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(CREQV,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(CRORC,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(CROR,(OP_REG bt, OP_REG ba, OP_REG bb));
|
||||
ADD_OPCODE(BCCTR,(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk));
|
||||
END_OPCODES_GROUP(G_13);
|
||||
|
||||
ADD_OPCODE(RLWIMI,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc));
|
||||
ADD_OPCODE(RLWINM,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc));
|
||||
ADD_OPCODE(RLWNM,(OP_REG ra, OP_REG rs, OP_REG rb, OP_REG MB, OP_REG ME, bool rc));
|
||||
ADD_OPCODE(ORI,(OP_REG rs, OP_REG ra, OP_uIMM uimm16));
|
||||
ADD_OPCODE(ORIS,(OP_REG rs, OP_REG ra, OP_uIMM uimm16));
|
||||
ADD_OPCODE(XORI,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
||||
ADD_OPCODE(XORIS,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
||||
ADD_OPCODE(ANDI_,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
||||
ADD_OPCODE(ANDIS_,(OP_REG ra, OP_REG rs, OP_uIMM uimm16));
|
||||
virtual void FCMPU(u32 bf, u32 fra, u32 frb) = 0;
|
||||
virtual void FRSP(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FCTIW(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FCTIWZ(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FDIV(u32 frd, u32 fra, u32 frb, bool rc) = 0;
|
||||
virtual void FSUB(u32 frd, u32 fra, u32 frb, bool rc) = 0;
|
||||
virtual void FADD(u32 frd, u32 fra, u32 frb, bool rc) = 0;
|
||||
virtual void FSQRT(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FMUL(u32 frd, u32 fra, u32 frc, bool rc) = 0;
|
||||
virtual void FRSQRTE(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0;
|
||||
virtual void FCMPO(u32 crfd, u32 fra, u32 frb) = 0;
|
||||
virtual void FNEG(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FMR(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FNABS(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FABS(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FCTID(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FCTIDZ(u32 frd, u32 frb, bool rc) = 0;
|
||||
virtual void FCFID(u32 frd, u32 frb, bool rc) = 0;
|
||||
|
||||
START_OPCODES_GROUP(G_1e)
|
||||
ADD_OPCODE(RLDICL,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc));
|
||||
ADD_OPCODE(RLDICR,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG me, bool rc));
|
||||
ADD_OPCODE(RLDIC,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc));
|
||||
ADD_OPCODE(RLDIMI,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc));
|
||||
END_OPCODES_GROUP(G_1e);
|
||||
|
||||
START_OPCODES_GROUP(G_1f)
|
||||
/*0x000*/ADD_OPCODE(CMP,(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb));
|
||||
/*0x004*/ADD_OPCODE(TW,(OP_uIMM to, OP_REG ra, OP_REG rb));
|
||||
/*0x006*/ADD_OPCODE(LVSL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x007*/ADD_OPCODE(LVEBX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x008*/ADD_OPCODE(SUBFC,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x009*/ADD_OPCODE(MULHDU,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
||||
/*0x00a*/ADD_OPCODE(ADDC,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x00b*/ADD_OPCODE(MULHWU,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
||||
/*0x013*/ADD_OPCODE(MFOCRF,(OP_uIMM a, OP_REG rd, OP_uIMM crm));
|
||||
/*0x014*/ADD_OPCODE(LWARX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x015*/ADD_OPCODE(LDX,(OP_REG ra, OP_REG rs, OP_REG rb));
|
||||
/*0x017*/ADD_OPCODE(LWZX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x018*/ADD_OPCODE(SLW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x01a*/ADD_OPCODE(CNTLZW,(OP_REG ra, OP_REG rs, bool rc));
|
||||
/*0x01b*/ADD_OPCODE(SLD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x01c*/ADD_OPCODE(AND,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x020*/ADD_OPCODE(CMPL,(OP_REG bf, OP_REG l, OP_REG ra, OP_REG rb));
|
||||
/*0x026*/ADD_OPCODE(LVSR,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x027*/ADD_OPCODE(LVEHX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x028*/ADD_OPCODE(SUBF,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x035*/ADD_OPCODE(LDUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x036*/ADD_OPCODE(DCBST,(OP_REG ra, OP_REG rb));
|
||||
/*0x03a*/ADD_OPCODE(CNTLZD,(OP_REG ra, OP_REG rs, bool rc));
|
||||
/*0x03c*/ADD_OPCODE(ANDC,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x047*/ADD_OPCODE(LVEWX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x049*/ADD_OPCODE(MULHD,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
||||
/*0x04b*/ADD_OPCODE(MULHW,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc));
|
||||
/*0x054*/ADD_OPCODE(LDARX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x056*/ADD_OPCODE(DCBF,(OP_REG ra, OP_REG rb));
|
||||
/*0x057*/ADD_OPCODE(LBZX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x067*/ADD_OPCODE(LVX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x068*/ADD_OPCODE(NEG,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
||||
/*0x077*/ADD_OPCODE(LBZUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x07c*/ADD_OPCODE(NOR,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x087*/ADD_OPCODE(STVEBX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x088*/ADD_OPCODE(SUBFE,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x08a*/ADD_OPCODE(ADDE,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x090*/ADD_OPCODE(MTOCRF,(OP_REG crm, OP_REG rs));
|
||||
/*0x095*/ADD_OPCODE(STDX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x096*/ADD_OPCODE(STWCX_,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x097*/ADD_OPCODE(STWX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x0a7*/ADD_OPCODE(STVEHX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x0b5*/ADD_OPCODE(STDUX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x0c7*/ADD_OPCODE(STVEWX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x0ca*/ADD_OPCODE(ADDZE,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
||||
/*0x0d6*/ADD_OPCODE(STDCX_,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x0d7*/ADD_OPCODE(STBX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x0e7*/ADD_OPCODE(STVX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x0e9*/ADD_OPCODE(MULLD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x0ea*/ADD_OPCODE(ADDME,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
||||
/*0x0eb*/ADD_OPCODE(MULLW,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x0f6*/ADD_OPCODE(DCBTST,(OP_REG th, OP_REG ra, OP_REG rb));
|
||||
/*0x10a*/ADD_OPCODE(ADD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x116*/ADD_OPCODE(DCBT,(OP_REG ra, OP_REG rb, OP_REG th));
|
||||
/*0x117*/ADD_OPCODE(LHZX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x11c*/ADD_OPCODE(EQV,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x136*/ADD_OPCODE(ECIWX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x137*/ADD_OPCODE(LHZUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x13c*/ADD_OPCODE(XOR,(OP_REG rs, OP_REG ra, OP_REG rb, bool rc));
|
||||
/*0x153*/ADD_OPCODE(MFSPR,(OP_REG rd, OP_REG spr));
|
||||
/*0x156*/ADD_OPCODE(DST,(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t));
|
||||
/*0x157*/ADD_OPCODE(LHAX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x167*/ADD_OPCODE(LVXL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x168*/ADD_OPCODE(ABS,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc));
|
||||
/*0x173*/ADD_OPCODE(MFTB,(OP_REG rd, OP_REG spr));
|
||||
/*0x176*/ADD_OPCODE(DSTST,(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t));
|
||||
/*0x177*/ADD_OPCODE(LHAUX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x197*/ADD_OPCODE(STHX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x19c*/ADD_OPCODE(ORC,(OP_REG rs, OP_REG ra, OP_REG rb, bool rc));
|
||||
/*0x1b6*/ADD_OPCODE(ECOWX,(OP_REG rs, OP_REG ra, OP_REG rb));
|
||||
/*0x1bc*/ADD_OPCODE(OR,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x1c9*/ADD_OPCODE(DIVDU,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x1cb*/ADD_OPCODE(DIVWU,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x1d3*/ADD_OPCODE(MTSPR,(OP_REG spr, OP_REG rs));
|
||||
/*0x1d6*///DCBI
|
||||
/*0x1dc*/ADD_OPCODE(NAND,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x1e7*/ADD_OPCODE(STVXL,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x1e9*/ADD_OPCODE(DIVD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x1eb*/ADD_OPCODE(DIVW,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc));
|
||||
/*0x207*/ADD_OPCODE(LVLX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x216*/ADD_OPCODE(LWBRX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x217*/ADD_OPCODE(LFSX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
||||
/*0x218*/ADD_OPCODE(SRW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x21b*/ADD_OPCODE(SRD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x227*/ADD_OPCODE(LVRX,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x237*/ADD_OPCODE(LFSUX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
||||
/*0x256*/ADD_OPCODE(SYNC,(OP_uIMM l));
|
||||
/*0x257*/ADD_OPCODE(LFDX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
||||
/*0x277*/ADD_OPCODE(LFDUX,(OP_REG frd, OP_REG ra, OP_REG rb));
|
||||
/*0x287*/ADD_OPCODE(STVLX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x297*/ADD_OPCODE(STFSX,(OP_REG frs, OP_REG ra, OP_REG rb));
|
||||
/*0x2a7*/ADD_OPCODE(STVRX,(OP_REG vs, OP_REG ra, OP_REG rb));
|
||||
/*0x2d7*/ADD_OPCODE(STFDX,(OP_REG frs, OP_REG ra, OP_REG rb));
|
||||
/*0x307*/ADD_OPCODE(LVLXL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x316*/ADD_OPCODE(LHBRX,(OP_REG rd, OP_REG ra, OP_REG rb));
|
||||
/*0x318*/ADD_OPCODE(SRAW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x31a*/ADD_OPCODE(SRAD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc));
|
||||
/*0x327*/ADD_OPCODE(LVRXL,(OP_REG vd, OP_REG ra, OP_REG rb));
|
||||
/*0x336*/ADD_OPCODE(DSS,(OP_uIMM strm, OP_uIMM a));
|
||||
/*0x338*/ADD_OPCODE(SRAWI,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc));
|
||||
/*0x33a*/ADD_OPCODE(SRADI1,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc));
|
||||
/*0x33b*/ADD_OPCODE(SRADI2,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc));
|
||||
/*0x356*/ADD_OPCODE(EIEIO,());
|
||||
/*0x387*/ADD_OPCODE(STVLXL,(OP_REG sd, OP_REG ra, OP_REG rb));
|
||||
/*0x39a*/ADD_OPCODE(EXTSH,(OP_REG ra, OP_REG rs, bool rc));
|
||||
/*0x3a7*/ADD_OPCODE(STVRXL,(OP_REG sd, OP_REG ra, OP_REG rb));
|
||||
/*0x3ba*/ADD_OPCODE(EXTSB,(OP_REG ra, OP_REG rs, bool rc));
|
||||
/*0x3d7*/ADD_OPCODE(STFIWX,(OP_REG frs, OP_REG ra, OP_REG rb));
|
||||
/*0x3da*/ADD_OPCODE(EXTSW,(OP_REG ra, OP_REG rs, bool rc));
|
||||
/*0x3d6*///ICBI
|
||||
/*0x3f6*/ADD_OPCODE(DCBZ,(OP_REG ra, OP_REG rb));
|
||||
END_OPCODES_GROUP(G_1f);
|
||||
|
||||
ADD_OPCODE(LWZ,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LWZU,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LBZ,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LBZU,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STW,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STWU,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STB,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STBU,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LHZ,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LHZU,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STH,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STHU,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LMW,(OP_REG rd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STMW,(OP_REG rs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LFS,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LFSU,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LFD,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(LFDU,(OP_REG frd, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STFS,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STFSU,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STFD,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
||||
ADD_OPCODE(STFDU,(OP_REG frs, OP_REG ra, OP_sIMM d));
|
||||
|
||||
START_OPCODES_GROUP(G_3a)
|
||||
ADD_OPCODE(LD,(OP_REG rd, OP_REG ra, OP_sIMM ds));
|
||||
ADD_OPCODE(LDU,(OP_REG rd, OP_REG ra, OP_sIMM ds));
|
||||
END_OPCODES_GROUP(G_3a);
|
||||
|
||||
START_OPCODES_GROUP(G_3b)
|
||||
ADD_OPCODE(FDIVS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FSUBS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FADDS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FSQRTS,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FRES,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FMULS,(OP_REG frd, OP_REG fra, OP_REG frc, bool rc));
|
||||
ADD_OPCODE(FMADDS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FMSUBS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FNMSUBS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FNMADDS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
END_OPCODES_GROUP(G_3b);
|
||||
|
||||
START_OPCODES_GROUP(G_3e)
|
||||
ADD_OPCODE(STD,(OP_REG rs, OP_REG ra, OP_sIMM ds));
|
||||
ADD_OPCODE(STDU,(OP_REG rs, OP_REG ra, OP_sIMM ds));
|
||||
END_OPCODES_GROUP(G_3e);
|
||||
|
||||
START_OPCODES_GROUP(G_3f)
|
||||
ADD_OPCODE(MTFSB1,(OP_REG bt, bool rc));
|
||||
ADD_OPCODE(MCRFS,(OP_REG bf, OP_REG bfa));
|
||||
ADD_OPCODE(MTFSB0,(OP_REG bt, bool rc));
|
||||
ADD_OPCODE(MTFSFI,(OP_REG crfd, OP_REG i, bool rc));
|
||||
ADD_OPCODE(MFFS,(OP_REG frd, bool rc));
|
||||
ADD_OPCODE(MTFSF,(OP_REG flm, OP_REG frb, bool rc));
|
||||
|
||||
ADD_OPCODE(FCMPU,(OP_REG bf, OP_REG fra, OP_REG frb));
|
||||
ADD_OPCODE(FRSP,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FCTIW,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FCTIWZ,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FDIV,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FSUB,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FADD,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FSQRT,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FSEL,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FMUL,(OP_REG frd, OP_REG fra, OP_REG frc, bool rc));
|
||||
ADD_OPCODE(FRSQRTE,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FMSUB,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FMADD,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FNMSUB,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FNMADD,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FCMPO,(OP_REG crfd, OP_REG fra, OP_REG frb));
|
||||
ADD_OPCODE(FNEG,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FMR,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FNABS,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FABS,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FCTID,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FCTIDZ,(OP_REG frd, OP_REG frb, bool rc));
|
||||
ADD_OPCODE(FCFID,(OP_REG frd, OP_REG frb, bool rc));
|
||||
END_OPCODES_GROUP(G_3f);
|
||||
|
||||
ADD_OPCODE(UNK,(const u32 code, const u32 opcode, const u32 gcode));
|
||||
virtual void UNK(const u32 code, const u32 opcode, const u32 gcode) = 0;
|
||||
};
|
||||
|
||||
//instr_caller* g_instrs[0x40];
|
||||
|
||||
#undef START_OPCODES_GROUP
|
||||
#undef ADD_OPCODE
|
||||
#undef ADD_NULL_OPCODE
|
||||
#undef END_OPCODES_GROUP
|
||||
@ -2,327 +2,26 @@
|
||||
|
||||
#include "Emu/Cell/SPUOpcodes.h"
|
||||
#include "Emu/Cell/PPCDecoder.h"
|
||||
|
||||
#define START_OPCODES_GROUP_(group, reg) \
|
||||
case(##group##): \
|
||||
temp=##reg##;\
|
||||
switch(temp)\
|
||||
{
|
||||
|
||||
#define START_OPCODES_GROUP(group, reg) START_OPCODES_GROUP_(##group##, ##reg##())
|
||||
|
||||
#define END_OPCODES_GROUP(group) \
|
||||
default:\
|
||||
m_op.UNK(m_code, opcode, temp);\
|
||||
break;\
|
||||
}\
|
||||
break
|
||||
|
||||
#define ADD_OPCODE(name, regs) case(##name##):m_op.##name####regs##; return
|
||||
#define ADD_NULL_OPCODE(name) ADD_OPCODE(##name##, ())
|
||||
#include "Emu/Cell/SPUInstrtable.h"
|
||||
|
||||
class SPU_Decoder : public PPC_Decoder
|
||||
{
|
||||
u32 m_code;
|
||||
SPU_Opcodes& m_op;
|
||||
|
||||
OP_REG RC() const { return GetField(4, 10); }
|
||||
OP_REG RT() const { return GetField(25, 31); }
|
||||
OP_REG RA() const { return GetField(18, 24); }
|
||||
OP_REG RB() const { return GetField(11, 17); }
|
||||
|
||||
OP_uIMM i7() const { return GetField(11, 17); }
|
||||
OP_uIMM i8() const { return GetField(10, 17); }
|
||||
OP_uIMM i10() const { return GetField(8, 17); }
|
||||
OP_uIMM i16() const { return GetField(9, 24); }
|
||||
OP_uIMM i18() const { return GetField(7, 24); }
|
||||
|
||||
OP_uIMM ROH() const { return GetField(16, 17); }
|
||||
OP_uIMM ROL() const { return GetField(25, 31); }
|
||||
OP_uIMM RO() const { return ROL() | (ROH() << 8); }
|
||||
|
||||
OP_uIMM RR() const { return GetField(0, 10); }
|
||||
OP_uIMM RRR() const { return GetField(0, 3); }
|
||||
OP_uIMM RI7() const { return GetField(0, 10); }
|
||||
OP_uIMM RI8() const { return GetField(0, 9); }
|
||||
OP_uIMM RI10() const { return GetField(0, 7); }
|
||||
OP_uIMM RI16() const { return GetField(0, 8); }
|
||||
OP_uIMM RI18() const { return GetField(0, 6); }
|
||||
|
||||
__forceinline u32 GetField(const u32 p) const
|
||||
{
|
||||
return (m_code >> (31 - p)) & 0x1;
|
||||
}
|
||||
|
||||
__forceinline u32 GetField(const u32 from, const u32 to) const
|
||||
{
|
||||
return (m_code >> (31 - to)) & ((1 << ((to - from) + 1)) - 1);
|
||||
}
|
||||
|
||||
OP_sIMM exts18(OP_sIMM i18) const
|
||||
{
|
||||
if(i18 & 0x20000) return i18 - 0x40000;
|
||||
return i18;
|
||||
}
|
||||
|
||||
OP_sIMM exts16(OP_sIMM i16) const
|
||||
{
|
||||
return (s32)(s16)i16;
|
||||
}
|
||||
|
||||
OP_sIMM exts10(OP_sIMM i10) const
|
||||
{
|
||||
if(i10 & 0x200) return i10 - 0x400;
|
||||
return i10;
|
||||
}
|
||||
|
||||
OP_sIMM exts7(OP_sIMM i7) const
|
||||
{
|
||||
if(i7 & 0x40) return i7 - 0x80;
|
||||
return i7;
|
||||
}
|
||||
SPU_Opcodes* m_op;
|
||||
|
||||
public:
|
||||
SPU_Decoder(SPU_Opcodes& op) : m_op(op)
|
||||
SPU_Decoder(SPU_Opcodes& op) : m_op(&op)
|
||||
{
|
||||
}
|
||||
|
||||
~SPU_Decoder()
|
||||
{
|
||||
m_op.Exit();
|
||||
delete &m_op;
|
||||
m_op->Exit();
|
||||
delete m_op;
|
||||
}
|
||||
|
||||
virtual void Decode(const u32 code)
|
||||
{
|
||||
using namespace SPU_opcodes;
|
||||
|
||||
m_code = code;
|
||||
|
||||
switch(RR()) //& RI7 //0 - 10
|
||||
{
|
||||
ADD_OPCODE(STOP,(GetField(18, 31)));
|
||||
ADD_OPCODE(LNOP,());
|
||||
ADD_OPCODE(SYNC,(GetField(11)));
|
||||
ADD_OPCODE(DSYNC,());
|
||||
ADD_OPCODE(MFSPR,(RT(), RA()));
|
||||
ADD_OPCODE(RDCH,(RT(), RA()));
|
||||
ADD_OPCODE(RCHCNT,(RT(), RA()));
|
||||
ADD_OPCODE(SF,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(OR,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(BG,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SFH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(NOR,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ABSDB,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTM,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTMA,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SHL,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTHM,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTMAH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SHLH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTMI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTMAI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SHLI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(ROTHI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(ROTHMI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(ROTMAHI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(SHLHI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(A,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(AND,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CG,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(AH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(NAND,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(AVGB,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MTSPR,(RT(), RA()));
|
||||
ADD_OPCODE(WRCH,(RA(), RT()));
|
||||
ADD_OPCODE(BIZ,(RT(), RA()));
|
||||
ADD_OPCODE(BINZ,(RT(), RA()));
|
||||
ADD_OPCODE(BIHZ,(RT(), RA()));
|
||||
ADD_OPCODE(BIHNZ,(RT(), RA()));
|
||||
ADD_OPCODE(STOPD,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(STQX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(BI,(RA()));
|
||||
ADD_OPCODE(BISL,(RT(), RA()));
|
||||
ADD_OPCODE(IRET,(RA()));
|
||||
ADD_OPCODE(BISLED,(RT(), RA()));
|
||||
ADD_OPCODE(HBR,(GetField(11), RO(), RA()));
|
||||
ADD_OPCODE(GB,(RT(), RA()));
|
||||
ADD_OPCODE(GBH,(RT(), RA()));
|
||||
ADD_OPCODE(GBB,(RT(), RA()));
|
||||
ADD_OPCODE(FSM,(RT(), RA()));
|
||||
ADD_OPCODE(FSMH,(RT(), RA()));
|
||||
ADD_OPCODE(FSMB,(RT(), RA()));
|
||||
ADD_OPCODE(FREST,(RT(), RA()));
|
||||
ADD_OPCODE(FRSQEST,(RT(), RA()));
|
||||
ADD_OPCODE(LQX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTQBYBI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTQMBYBI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SHLQBYBI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CBX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CHX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CWX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CDX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTQBI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTQMBI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SHLQBI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTQBY,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ROTQMBY,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SHLQBY,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ORX,(RT(), RA()));
|
||||
ADD_OPCODE(CBD,(RT(), RA(), exts7(i7())));
|
||||
ADD_OPCODE(CHD,(RT(), RA(), exts7(i7())));
|
||||
ADD_OPCODE(CWD,(RT(), RA(), exts7(i7())));
|
||||
ADD_OPCODE(CDD,(RT(), RA(), exts7(i7())));
|
||||
ADD_OPCODE(ROTQBII,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(ROTQMBII,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(SHLQBII,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(ROTQBYI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(ROTQMBYI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(SHLQBYI,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(NOP,(RT()));
|
||||
ADD_OPCODE(CGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(XOR,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CGTH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(EQV,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CGTB,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SUMB,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(HGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CLZ,(RT(), RA()));
|
||||
ADD_OPCODE(XSWD,(RT(), RA()));
|
||||
ADD_OPCODE(XSHW,(RT(), RA()));
|
||||
ADD_OPCODE(CNTB,(RT(), RA()));
|
||||
ADD_OPCODE(XSBH,(RT(), RA()));
|
||||
ADD_OPCODE(CLGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ANDC,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FCGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFCGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FA,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FS,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FM,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CLGTH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ORC,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FCMGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFCMGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFA,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFS,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFM,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CLGTB,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(HLGT,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFMA,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFMS,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFNMS,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFNMA,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CEQ,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYHHU,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(ADDX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(SFX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CGX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(BGX,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYHHA,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYHHAU,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FSCRRD,(RT()));
|
||||
ADD_OPCODE(FESD,(RT(), RA()));
|
||||
ADD_OPCODE(FRDS,(RT(), RA()));
|
||||
ADD_OPCODE(FSCRWR,(RT(), RA()));
|
||||
ADD_OPCODE(DFTSV,(RT(), RA(), i7()));
|
||||
ADD_OPCODE(FCEQ,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFCEQ,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPY,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYHH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYS,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CEQH,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FCMEQ,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(DFCMEQ,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(MPYU,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(CEQB,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(FI,(RT(), RA(), RB()));
|
||||
ADD_OPCODE(HEQ,(RT(), RA(), RB()));
|
||||
}
|
||||
|
||||
switch(RI8()) //0 - 9
|
||||
{
|
||||
ADD_OPCODE(CFLTS,(RT(), RA(), i8()));
|
||||
ADD_OPCODE(CFLTU,(RT(), RA(), i8()));
|
||||
ADD_OPCODE(CSFLT,(RT(), RA(), i8()));
|
||||
ADD_OPCODE(CUFLT,(RT(), RA(), i8()));
|
||||
}
|
||||
|
||||
switch(RI16()) //0 - 8
|
||||
{
|
||||
ADD_OPCODE(BRZ,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(STQA,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(BRNZ,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(BRHZ,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(BRHNZ,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(STQR,(RT(), i16()));
|
||||
ADD_OPCODE(BRA,(exts16(i16())));
|
||||
ADD_OPCODE(LQA,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(BRASL,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(BR,(exts16(i16())));
|
||||
ADD_OPCODE(FSMBI,(RT(), i16()));
|
||||
ADD_OPCODE(BRSL,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(LQR,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(IL,(RT(), exts16(i16())));
|
||||
ADD_OPCODE(ILHU,(RT(), i16()));
|
||||
ADD_OPCODE(ILH,(RT(), i16()));
|
||||
ADD_OPCODE(IOHL,(RT(), i16()));
|
||||
}
|
||||
|
||||
switch(RI10()) //0 - 7
|
||||
{
|
||||
ADD_OPCODE(ORI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(ORHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(ORBI,(RT(), RA(), i10()));
|
||||
ADD_OPCODE(SFI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(SFHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(ANDI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(ANDHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(ANDBI,(RT(), RA(), i10()));
|
||||
ADD_OPCODE(AI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(AHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(STQD,(RT(), exts10(i10()) << 4, RA()));
|
||||
ADD_OPCODE(LQD,(RT(), exts10(i10()) << 4, RA()));
|
||||
ADD_OPCODE(XORI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(XORHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(XORBI,(RT(), RA(), i10()));
|
||||
ADD_OPCODE(CGTI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CGTHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CGTBI,(RT(), RA(), i10()));
|
||||
ADD_OPCODE(HGTI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CLGTI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CLGTHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CLGTBI,(RT(), RA(), i10()));
|
||||
ADD_OPCODE(HLGTI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(MPYI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(MPYUI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CEQI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CEQHI,(RT(), RA(), exts10(i10())));
|
||||
ADD_OPCODE(CEQBI,(RT(), RA(), i10()));
|
||||
ADD_OPCODE(HEQI,(RT(), RA(), exts10(i10())));
|
||||
}
|
||||
|
||||
switch(RI18()) //0 - 6
|
||||
{
|
||||
ADD_OPCODE(HBRA,(RO(), i16() << 2));
|
||||
ADD_OPCODE(HBRR,(RO(), exts16(i16())));
|
||||
ADD_OPCODE(ILA,(RT(), i18()));
|
||||
}
|
||||
|
||||
switch(RRR()) //0 - 3
|
||||
{
|
||||
ADD_OPCODE(SELB,(RC(), RA(), RB(), RT()));
|
||||
ADD_OPCODE(SHUFB,(RC(), RA(), RB(), RT()));
|
||||
ADD_OPCODE(MPYA,(RC(), RA(), RB(), RT()));
|
||||
ADD_OPCODE(FNMS,(RC(), RA(), RB(), RT()));
|
||||
ADD_OPCODE(FMA,(RC(), RA(), RB(), RT()));
|
||||
ADD_OPCODE(FMS,(RC(), RA(), RB(), RT()));
|
||||
}
|
||||
|
||||
m_op.UNK(m_code, 0, 0);
|
||||
(*SPU_instr::rrr_list)(m_op, code);
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
258
rpcs3/Emu/Cell/SPUInstrTable.h
Normal file
258
rpcs3/Emu/Cell/SPUInstrTable.h
Normal file
@ -0,0 +1,258 @@
|
||||
#pragma once
|
||||
#include "PPCInstrTable.h"
|
||||
#include "PPCDecoder.h"
|
||||
#include "SPUOpcodes.h"
|
||||
|
||||
namespace SPU_instr
|
||||
{
|
||||
static CodeField<4, 10> RC(FIELD_R_GPR);
|
||||
static CodeField<25, 31> RT(FIELD_R_GPR);
|
||||
static CodeField<18, 24> RA(FIELD_R_GPR);
|
||||
static CodeField<11, 17> RB(FIELD_R_GPR);
|
||||
|
||||
static CodeField<11, 17> i7;
|
||||
static CodeField<10, 17> i8;
|
||||
static CodeField<8, 17> i10;
|
||||
static CodeField<9, 24> i16;
|
||||
static CodeField<7, 24> i18;
|
||||
|
||||
static CodeFieldSigned<11, 17> si7;
|
||||
static CodeFieldSigned<10, 17> si8;
|
||||
static CodeFieldSigned<8, 17> si10;
|
||||
static CodeFieldSignedOffset<8, 17, 4> si10s4;
|
||||
static CodeFieldSigned<9, 24> si16;
|
||||
static CodeFieldOffset<9, 24, 2> i16s2;
|
||||
static CodeFieldSigned<7, 24> si18;
|
||||
|
||||
static CodeField<16, 17> ROH;
|
||||
static CodeField<25, 31> ROL;
|
||||
static DoubleCodeField<16, 17, 25, 31, 8> RO;
|
||||
|
||||
static CodeField<0, 3> RRR;
|
||||
static CodeField<0, 6> RI18;
|
||||
static CodeField<0, 7> RI10;
|
||||
static CodeField<0, 8> RI16;
|
||||
static CodeField<0, 9> RI8;
|
||||
static CodeField<0, 10> RI7;
|
||||
static CodeField<0, 10> RR;
|
||||
|
||||
static CodeField<18, 31> L_18_31;
|
||||
static CodeField<11> L_11;
|
||||
|
||||
static auto rrr_list = new_list<SPU_Opcodes>(RRR);
|
||||
static auto ri18_list = new_list(rrr_list, RI18);
|
||||
static auto ri10_list = new_list(ri18_list, RI10);
|
||||
static auto ri16_list = new_list(ri10_list, RI16);
|
||||
static auto ri8_list = new_list(ri16_list, RI8);
|
||||
static auto ri7_list = new_list(ri8_list, RI7, instr_bind(&SPU_Opcodes::UNK, GetCode, RRR, RI7));
|
||||
|
||||
#define bind_instr(list, name, ...) \
|
||||
static const auto& name = make_instr<SPU_opcodes::name>(list, #name, &SPU_Opcodes::name, ##__VA_ARGS__)
|
||||
|
||||
bind_instr(ri7_list, STOP, L_18_31);
|
||||
bind_instr(ri7_list, LNOP);
|
||||
bind_instr(ri7_list, SYNC, L_11);
|
||||
bind_instr(ri7_list, DSYNC);
|
||||
bind_instr(ri7_list, MFSPR, RT, RA);
|
||||
bind_instr(ri7_list, RDCH, RT, RA);
|
||||
bind_instr(ri7_list, RCHCNT, RT, RA);
|
||||
bind_instr(ri7_list, SF, RT, RA, RB);
|
||||
bind_instr(ri7_list, OR, RT, RA, RB);
|
||||
bind_instr(ri7_list, BG, RT, RA, RB);
|
||||
bind_instr(ri7_list, SFH, RT, RA, RB);
|
||||
bind_instr(ri7_list, NOR, RT, RA, RB);
|
||||
bind_instr(ri7_list, ABSDB, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROT, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTM, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTMA, RT, RA, RB);
|
||||
bind_instr(ri7_list, SHL, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTH, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTHM, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTMAH, RT, RA, RB);
|
||||
bind_instr(ri7_list, SHLH, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTI, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTMI, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTMAI, RT, RA, RB);
|
||||
bind_instr(ri7_list, SHLI, RT, RA, i7);
|
||||
bind_instr(ri7_list, ROTHI, RT, RA, i7);
|
||||
bind_instr(ri7_list, ROTHMI, RT, RA, i7);
|
||||
bind_instr(ri7_list, ROTMAHI, RT, RA, i7);
|
||||
bind_instr(ri7_list, SHLHI, RT, RA, i7);
|
||||
bind_instr(ri7_list, A, RT, RA, RB);
|
||||
bind_instr(ri7_list, AND, RT, RA, RB);
|
||||
bind_instr(ri7_list, CG, RT, RA, RB);
|
||||
bind_instr(ri7_list, AH, RT, RA, RB);
|
||||
bind_instr(ri7_list, NAND, RT, RA, RB);
|
||||
bind_instr(ri7_list, AVGB, RT, RA, RB);
|
||||
bind_instr(ri7_list, MTSPR, RT, RA);
|
||||
bind_instr(ri7_list, WRCH, RA, RT);
|
||||
bind_instr(ri7_list, BIZ, RT, RA);
|
||||
bind_instr(ri7_list, BINZ, RT, RA);
|
||||
bind_instr(ri7_list, BIHZ, RT, RA);
|
||||
bind_instr(ri7_list, BIHNZ, RT, RA);
|
||||
bind_instr(ri7_list, STOPD, RT, RA, RB);
|
||||
bind_instr(ri7_list, STQX, RT, RA, RB);
|
||||
bind_instr(ri7_list, BI, RA);
|
||||
bind_instr(ri7_list, BISL, RT, RA);
|
||||
bind_instr(ri7_list, IRET, RA);
|
||||
bind_instr(ri7_list, BISLED, RT, RA);
|
||||
bind_instr(ri7_list, HBR, L_11, RO, RA);
|
||||
bind_instr(ri7_list, GB, RT, RA);
|
||||
bind_instr(ri7_list, GBH, RT, RA);
|
||||
bind_instr(ri7_list, GBB, RT, RA);
|
||||
bind_instr(ri7_list, FSM, RT, RA);
|
||||
bind_instr(ri7_list, FSMH, RT, RA);
|
||||
bind_instr(ri7_list, FSMB, RT, RA);
|
||||
bind_instr(ri7_list, FREST, RT, RA);
|
||||
bind_instr(ri7_list, FRSQEST, RT, RA);
|
||||
bind_instr(ri7_list, LQX, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTQBYBI, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTQMBYBI, RT, RA, RB);
|
||||
bind_instr(ri7_list, SHLQBYBI, RT, RA, RB);
|
||||
bind_instr(ri7_list, CBX, RT, RA, RB);
|
||||
bind_instr(ri7_list, CHX, RT, RA, RB);
|
||||
bind_instr(ri7_list, CWX, RT, RA, RB);
|
||||
bind_instr(ri7_list, CDX, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTQBI, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTQMBI, RT, RA, RB);
|
||||
bind_instr(ri7_list, SHLQBI, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTQBY, RT, RA, RB);
|
||||
bind_instr(ri7_list, ROTQMBY, RT, RA, RB);
|
||||
bind_instr(ri7_list, SHLQBY, RT, RA, RB);
|
||||
bind_instr(ri7_list, ORX, RT, RA);
|
||||
bind_instr(ri7_list, CBD, RT, RA, si7);
|
||||
bind_instr(ri7_list, CHD, RT, RA, si7);
|
||||
bind_instr(ri7_list, CWD, RT, RA, si7);
|
||||
bind_instr(ri7_list, CDD, RT, RA, si7);
|
||||
bind_instr(ri7_list, ROTQBII, RT, RA, i7);
|
||||
bind_instr(ri7_list, ROTQMBII, RT, RA, i7);
|
||||
bind_instr(ri7_list, SHLQBII, RT, RA, i7);
|
||||
bind_instr(ri7_list, ROTQBYI, RT, RA, i7);
|
||||
bind_instr(ri7_list, ROTQMBYI, RT, RA, i7);
|
||||
bind_instr(ri7_list, SHLQBYI, RT, RA, i7);
|
||||
bind_instr(ri7_list, NOP, RT);
|
||||
bind_instr(ri7_list, CGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, XOR, RT, RA, RB);
|
||||
bind_instr(ri7_list, CGTH, RT, RA, RB);
|
||||
bind_instr(ri7_list, EQV, RT, RA, RB);
|
||||
bind_instr(ri7_list, CGTB, RT, RA, RB);
|
||||
bind_instr(ri7_list, SUMB, RT, RA, RB);
|
||||
bind_instr(ri7_list, HGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, CLZ, RT, RA);
|
||||
bind_instr(ri7_list, XSWD, RT, RA);
|
||||
bind_instr(ri7_list, XSHW, RT, RA);
|
||||
bind_instr(ri7_list, CNTB, RT, RA);
|
||||
bind_instr(ri7_list, XSBH, RT, RA);
|
||||
bind_instr(ri7_list, CLGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, ANDC, RT, RA, RB);
|
||||
bind_instr(ri7_list, FCGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFCGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, FA, RT, RA, RB);
|
||||
bind_instr(ri7_list, FS, RT, RA, RB);
|
||||
bind_instr(ri7_list, FM, RT, RA, RB);
|
||||
bind_instr(ri7_list, CLGTH, RT, RA, RB);
|
||||
bind_instr(ri7_list, ORC, RT, RA, RB);
|
||||
bind_instr(ri7_list, FCMGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFCMGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFA, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFS, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFM, RT, RA, RB);
|
||||
bind_instr(ri7_list, CLGTB, RT, RA, RB);
|
||||
bind_instr(ri7_list, HLGT, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFMA, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFMS, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFNMS, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFNMA, RT, RA, RB);
|
||||
bind_instr(ri7_list, CEQ, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYHHU, RT, RA, RB);
|
||||
bind_instr(ri7_list, ADDX, RT, RA, RB);
|
||||
bind_instr(ri7_list, SFX, RT, RA, RB);
|
||||
bind_instr(ri7_list, CGX, RT, RA, RB);
|
||||
bind_instr(ri7_list, BGX, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYHHA, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYHHAU, RT, RA, RB);
|
||||
bind_instr(ri7_list, FSCRRD, RT);
|
||||
bind_instr(ri7_list, FESD, RT, RA);
|
||||
bind_instr(ri7_list, FRDS, RT, RA);
|
||||
bind_instr(ri7_list, FSCRWR, RT, RA);
|
||||
bind_instr(ri7_list, DFTSV, RT, RA, i7);
|
||||
bind_instr(ri7_list, FCEQ, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFCEQ, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPY, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYH, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYHH, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYS, RT, RA, RB);
|
||||
bind_instr(ri7_list, CEQH, RT, RA, RB);
|
||||
bind_instr(ri7_list, FCMEQ, RT, RA, RB);
|
||||
bind_instr(ri7_list, DFCMEQ, RT, RA, RB);
|
||||
bind_instr(ri7_list, MPYU, RT, RA, RB);
|
||||
bind_instr(ri7_list, CEQB, RT, RA, RB);
|
||||
bind_instr(ri7_list, FI, RT, RA, RB);
|
||||
bind_instr(ri7_list, HEQ, RT, RA, RB);
|
||||
|
||||
bind_instr(ri8_list, CFLTS, RT, RA, i8);
|
||||
bind_instr(ri8_list, CFLTU, RT, RA, i8);
|
||||
bind_instr(ri8_list, CSFLT, RT, RA, i8);
|
||||
bind_instr(ri8_list, CUFLT, RT, RA, i8);
|
||||
|
||||
bind_instr(ri16_list, BRZ, RT, si16);
|
||||
bind_instr(ri16_list, STQA, RT, si16);
|
||||
bind_instr(ri16_list, BRNZ, RT, si16);
|
||||
bind_instr(ri16_list, BRHZ, RT, si16);
|
||||
bind_instr(ri16_list, BRHNZ, RT, si16);
|
||||
bind_instr(ri16_list, STQR, RT, i16);
|
||||
bind_instr(ri16_list, BRA, si16);
|
||||
bind_instr(ri16_list, LQA, RT, si16);
|
||||
bind_instr(ri16_list, BRASL, RT, si16);
|
||||
bind_instr(ri16_list, BR, si16);
|
||||
bind_instr(ri16_list, FSMBI, RT, i16);
|
||||
bind_instr(ri16_list, BRSL, RT, si16);
|
||||
bind_instr(ri16_list, LQR, RT, si16);
|
||||
bind_instr(ri16_list, IL, RT, si16);
|
||||
bind_instr(ri16_list, ILHU, RT, i16);
|
||||
bind_instr(ri16_list, ILH, RT, i16);
|
||||
bind_instr(ri16_list, IOHL, RT, i16);
|
||||
|
||||
bind_instr(ri10_list, ORI, RT, RA, si10);
|
||||
bind_instr(ri10_list, ORHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, ORBI, RT, RA, i10);
|
||||
bind_instr(ri10_list, SFI, RT, RA, si10);
|
||||
bind_instr(ri10_list, SFHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, ANDI, RT, RA, si10);
|
||||
bind_instr(ri10_list, ANDHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, ANDBI, RT, RA, i10);
|
||||
bind_instr(ri10_list, AI, RT, RA, si10);
|
||||
bind_instr(ri10_list, AHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, STQD, RT, si10s4, RA);
|
||||
bind_instr(ri10_list, LQD, RT, si10s4, RA);
|
||||
bind_instr(ri10_list, XORI, RT, RA, si10);
|
||||
bind_instr(ri10_list, XORHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, XORBI, RT, RA, i10);
|
||||
bind_instr(ri10_list, CGTI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CGTHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CGTBI, RT, RA, i10);
|
||||
bind_instr(ri10_list, HGTI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CLGTI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CLGTHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CLGTBI, RT, RA, i10);
|
||||
bind_instr(ri10_list, HLGTI, RT, RA, si10);
|
||||
bind_instr(ri10_list, MPYI, RT, RA, si10);
|
||||
bind_instr(ri10_list, MPYUI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CEQI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CEQHI, RT, RA, si10);
|
||||
bind_instr(ri10_list, CEQBI, RT, RA, i10);
|
||||
bind_instr(ri10_list, HEQI, RT, RA, si10);
|
||||
|
||||
bind_instr(ri18_list, HBRA, RO, i16s2);
|
||||
bind_instr(ri18_list, HBRR, RO, si16);
|
||||
bind_instr(ri18_list, ILA, RT, i18);
|
||||
|
||||
bind_instr(rrr_list, SELB, RC, RA, RB, RT);
|
||||
bind_instr(rrr_list, SHUFB, RC, RA, RB, RT);
|
||||
bind_instr(rrr_list, MPYA, RC, RA, RB, RT);
|
||||
bind_instr(rrr_list, FNMS, RC, RA, RB, RT);
|
||||
bind_instr(rrr_list, FMA, RC, RA, RB, RT);
|
||||
bind_instr(rrr_list, FMS, RC, RA, RB, RT);
|
||||
|
||||
#undef bind_instr
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,13 +1,5 @@
|
||||
#pragma once
|
||||
|
||||
#define OP_REG u32
|
||||
#define OP_sIMM s32
|
||||
#define OP_uIMM u32
|
||||
#define START_OPCODES_GROUP(x) /*x*/
|
||||
#define ADD_OPCODE(name, regs) virtual void(##name##)##regs##=0
|
||||
#define ADD_NULL_OPCODE(name) virtual void(##name##)()=0
|
||||
#define END_OPCODES_GROUP(x) /*x*/
|
||||
|
||||
namespace SPU_opcodes
|
||||
{
|
||||
enum SPU_0_10_Opcodes
|
||||
@ -245,220 +237,215 @@ public:
|
||||
virtual void Exit()=0;
|
||||
|
||||
//0 - 10
|
||||
ADD_OPCODE(STOP,(OP_uIMM code));
|
||||
ADD_OPCODE(LNOP,());
|
||||
ADD_OPCODE(SYNC, (OP_uIMM Cbit));
|
||||
ADD_OPCODE(DSYNC, ());
|
||||
ADD_OPCODE(MFSPR,(OP_REG rt, OP_REG sa));
|
||||
ADD_OPCODE(RDCH,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(RCHCNT,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(SF,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(OR,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(BG,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SFH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(NOR,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ABSDB,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTM,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTMA,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SHL,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTHM,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTMAH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SHLH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTMI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTMAI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(SHLI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTHI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTHMI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTMAHI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(SHLHI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(A,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(AND,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CG,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(AH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(NAND,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(AVGB,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MTSPR,(OP_REG rt, OP_REG sa));
|
||||
ADD_OPCODE(WRCH,(OP_REG ra, OP_REG rt));
|
||||
ADD_OPCODE(BIZ,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(BINZ,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(BIHZ,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(BIHNZ,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(STOPD,(OP_REG rc, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(STQX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(BI,(OP_REG ra));
|
||||
ADD_OPCODE(BISL,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(IRET,(OP_REG ra));
|
||||
ADD_OPCODE(BISLED,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(HBR,(OP_REG p, OP_REG ro, OP_REG ra));
|
||||
ADD_OPCODE(GB,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(GBH,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(GBB,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FSM,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FSMH,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FSMB,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FREST,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FRSQEST,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(LQX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTQBYBI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTQMBYBI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SHLQBYBI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CBX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CHX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CWX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CDX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTQBI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTQMBI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SHLQBI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTQBY,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ROTQMBY,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SHLQBY,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ORX,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(CBD,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(CHD,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(CWD,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(CDD,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTQBII,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTQMBII,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(SHLQBII,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTQBYI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(ROTQMBYI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(SHLQBYI,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(NOP,(OP_REG rt));
|
||||
ADD_OPCODE(CGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(XOR,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CGTH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(EQV,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CGTB,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SUMB,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(HGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CLZ,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(XSWD,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(XSHW,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(CNTB,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(XSBH,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(CLGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ANDC,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FCGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFCGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FA,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FS,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FM,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CLGTH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ORC,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FCMGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFCMGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFA,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFS,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFM,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CLGTB,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(HLGT,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFMA,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFMS,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFNMS,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFNMA,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CEQ,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYHHU,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(ADDX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(SFX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CGX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(BGX,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYHHA,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYHHAU,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FSCRRD,(OP_REG rt));
|
||||
ADD_OPCODE(FESD,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FRDS,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(FSCRWR,(OP_REG rt, OP_REG ra));
|
||||
ADD_OPCODE(DFTSV,(OP_REG rt, OP_REG ra, OP_sIMM i7));
|
||||
ADD_OPCODE(FCEQ,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFCEQ,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPY,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYHH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYS,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CEQH,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FCMEQ,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(DFCMEQ,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(MPYU,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(CEQB,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(FI,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
ADD_OPCODE(HEQ,(OP_REG rt, OP_REG ra, OP_REG rb));
|
||||
virtual void STOP(u32 code) = 0;
|
||||
virtual void LNOP() = 0;
|
||||
virtual void SYNC(u32 Cbit) = 0;
|
||||
virtual void DSYNC() = 0;
|
||||
virtual void MFSPR(u32 rt, u32 sa) = 0;
|
||||
virtual void RDCH(u32 rt, u32 ra) = 0;
|
||||
virtual void RCHCNT(u32 rt, u32 ra) = 0;
|
||||
virtual void SF(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void OR(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void BG(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SFH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void NOR(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ABSDB(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTM(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTMA(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SHL(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTHM(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTMAH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SHLH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTMI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTMAI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void SHLI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTHI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTHMI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTMAHI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void SHLHI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void A(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void AND(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CG(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void AH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void NAND(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void AVGB(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MTSPR(u32 rt, u32 sa) = 0;
|
||||
virtual void WRCH(u32 ra, u32 rt) = 0;
|
||||
virtual void BIZ(u32 rt, u32 ra) = 0;
|
||||
virtual void BINZ(u32 rt, u32 ra) = 0;
|
||||
virtual void BIHZ(u32 rt, u32 ra) = 0;
|
||||
virtual void BIHNZ(u32 rt, u32 ra) = 0;
|
||||
virtual void STOPD(u32 rc, u32 ra, u32 rb) = 0;
|
||||
virtual void STQX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void BI(u32 ra) = 0;
|
||||
virtual void BISL(u32 rt, u32 ra) = 0;
|
||||
virtual void IRET(u32 ra) = 0;
|
||||
virtual void BISLED(u32 rt, u32 ra) = 0;
|
||||
virtual void HBR(u32 p, u32 ro, u32 ra) = 0;
|
||||
virtual void GB(u32 rt, u32 ra) = 0;
|
||||
virtual void GBH(u32 rt, u32 ra) = 0;
|
||||
virtual void GBB(u32 rt, u32 ra) = 0;
|
||||
virtual void FSM(u32 rt, u32 ra) = 0;
|
||||
virtual void FSMH(u32 rt, u32 ra) = 0;
|
||||
virtual void FSMB(u32 rt, u32 ra) = 0;
|
||||
virtual void FREST(u32 rt, u32 ra) = 0;
|
||||
virtual void FRSQEST(u32 rt, u32 ra) = 0;
|
||||
virtual void LQX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTQBYBI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTQMBYBI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SHLQBYBI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CBX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CHX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CWX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CDX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTQBI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTQMBI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SHLQBI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTQBY(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ROTQMBY(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SHLQBY(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ORX(u32 rt, u32 ra) = 0;
|
||||
virtual void CBD(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void CHD(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void CWD(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void CDD(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTQBII(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTQMBII(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void SHLQBII(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTQBYI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void ROTQMBYI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void SHLQBYI(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void NOP(u32 rt) = 0;
|
||||
virtual void CGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void XOR(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CGTH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void EQV(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CGTB(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SUMB(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void HGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CLZ(u32 rt, u32 ra) = 0;
|
||||
virtual void XSWD(u32 rt, u32 ra) = 0;
|
||||
virtual void XSHW(u32 rt, u32 ra) = 0;
|
||||
virtual void CNTB(u32 rt, u32 ra) = 0;
|
||||
virtual void XSBH(u32 rt, u32 ra) = 0;
|
||||
virtual void CLGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ANDC(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FCGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFCGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FA(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FS(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FM(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CLGTH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ORC(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FCMGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFCMGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFA(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFS(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFM(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CLGTB(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void HLGT(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFMA(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFMS(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFNMS(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFNMA(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CEQ(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYHHU(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void ADDX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void SFX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CGX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void BGX(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYHHA(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYHHAU(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FSCRRD(u32 rt) = 0;
|
||||
virtual void FESD(u32 rt, u32 ra) = 0;
|
||||
virtual void FRDS(u32 rt, u32 ra) = 0;
|
||||
virtual void FSCRWR(u32 rt, u32 ra) = 0;
|
||||
virtual void DFTSV(u32 rt, u32 ra, s32 i7) = 0;
|
||||
virtual void FCEQ(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFCEQ(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPY(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYHH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYS(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CEQH(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FCMEQ(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void DFCMEQ(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void MPYU(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void CEQB(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void FI(u32 rt, u32 ra, u32 rb) = 0;
|
||||
virtual void HEQ(u32 rt, u32 ra, u32 rb) = 0;
|
||||
|
||||
//0 - 9
|
||||
ADD_OPCODE(CFLTS,(OP_REG rt, OP_REG ra, OP_sIMM i8));
|
||||
ADD_OPCODE(CFLTU,(OP_REG rt, OP_REG ra, OP_sIMM i8));
|
||||
ADD_OPCODE(CSFLT,(OP_REG rt, OP_REG ra, OP_sIMM i8));
|
||||
ADD_OPCODE(CUFLT,(OP_REG rt, OP_REG ra, OP_sIMM i8));
|
||||
virtual void CFLTS(u32 rt, u32 ra, s32 i8) = 0;
|
||||
virtual void CFLTU(u32 rt, u32 ra, s32 i8) = 0;
|
||||
virtual void CSFLT(u32 rt, u32 ra, s32 i8) = 0;
|
||||
virtual void CUFLT(u32 rt, u32 ra, s32 i8) = 0;
|
||||
|
||||
//0 - 8
|
||||
ADD_OPCODE(BRZ,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(STQA,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BRNZ,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BRHZ,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BRHNZ,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(STQR,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BRA,(OP_sIMM i16));
|
||||
ADD_OPCODE(LQA,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BRASL,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BR,(OP_sIMM i16));
|
||||
ADD_OPCODE(FSMBI,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(BRSL,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(LQR,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(IL,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(ILHU,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(ILH,(OP_REG rt, OP_sIMM i16));
|
||||
ADD_OPCODE(IOHL,(OP_REG rt, OP_sIMM i16));
|
||||
virtual void BRZ(u32 rt, s32 i16) = 0;
|
||||
virtual void STQA(u32 rt, s32 i16) = 0;
|
||||
virtual void BRNZ(u32 rt, s32 i16) = 0;
|
||||
virtual void BRHZ(u32 rt, s32 i16) = 0;
|
||||
virtual void BRHNZ(u32 rt, s32 i16) = 0;
|
||||
virtual void STQR(u32 rt, s32 i16) = 0;
|
||||
virtual void BRA(s32 i16) = 0;
|
||||
virtual void LQA(u32 rt, s32 i16) = 0;
|
||||
virtual void BRASL(u32 rt, s32 i16) = 0;
|
||||
virtual void BR(s32 i16) = 0;
|
||||
virtual void FSMBI(u32 rt, s32 i16) = 0;
|
||||
virtual void BRSL(u32 rt, s32 i16) = 0;
|
||||
virtual void LQR(u32 rt, s32 i16) = 0;
|
||||
virtual void IL(u32 rt, s32 i16) = 0;
|
||||
virtual void ILHU(u32 rt, s32 i16) = 0;
|
||||
virtual void ILH(u32 rt, s32 i16) = 0;
|
||||
virtual void IOHL(u32 rt, s32 i16) = 0;
|
||||
|
||||
//0 - 7
|
||||
ADD_OPCODE(ORI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(ORHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(ORBI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(SFI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(SFHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(ANDI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(ANDHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(ANDBI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(AI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(AHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(STQD,(OP_REG rt, OP_sIMM i10, OP_REG ra));
|
||||
ADD_OPCODE(LQD,(OP_REG rt, OP_sIMM i10, OP_REG ra));
|
||||
ADD_OPCODE(XORI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(XORHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(XORBI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CGTHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CGTBI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(HGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CLGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CLGTHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CLGTBI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(HLGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(MPYI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(MPYUI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CEQI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CEQHI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(CEQBI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
ADD_OPCODE(HEQI,(OP_REG rt, OP_REG ra, OP_sIMM i10));
|
||||
virtual void ORI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void ORHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void ORBI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void SFI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void SFHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void ANDI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void ANDHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void ANDBI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void AI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void AHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void STQD(u32 rt, s32 i10, u32 ra) = 0;
|
||||
virtual void LQD(u32 rt, s32 i10, u32 ra) = 0;
|
||||
virtual void XORI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void XORHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void XORBI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CGTI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CGTHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CGTBI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void HGTI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CLGTI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CLGTHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CLGTBI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void HLGTI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void MPYI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void MPYUI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CEQI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CEQHI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void CEQBI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
virtual void HEQI(u32 rt, u32 ra, s32 i10) = 0;
|
||||
|
||||
//0 - 6
|
||||
ADD_OPCODE(HBRA,(OP_sIMM ro, OP_sIMM i16));
|
||||
ADD_OPCODE(HBRR,(OP_sIMM ro, OP_sIMM i16));
|
||||
ADD_OPCODE(ILA,(OP_REG rt, OP_sIMM i18));
|
||||
virtual void HBRA(s32 ro, s32 i16) = 0;
|
||||
virtual void HBRR(s32 ro, s32 i16) = 0;
|
||||
virtual void ILA(u32 rt, s32 i18) = 0;
|
||||
|
||||
//0 - 3
|
||||
ADD_OPCODE(SELB,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt));
|
||||
ADD_OPCODE(SHUFB,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt));
|
||||
ADD_OPCODE(MPYA,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt));
|
||||
ADD_OPCODE(FNMS,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt));
|
||||
ADD_OPCODE(FMA,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt));
|
||||
ADD_OPCODE(FMS,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt));
|
||||
virtual void SELB(u32 rc, u32 ra, u32 rb, u32 rt) = 0;
|
||||
virtual void SHUFB(u32 rc, u32 ra, u32 rb, u32 rt) = 0;
|
||||
virtual void MPYA(u32 rc, u32 ra, u32 rb, u32 rt) = 0;
|
||||
virtual void FNMS(u32 rc, u32 ra, u32 rb, u32 rt) = 0;
|
||||
virtual void FMA(u32 rc, u32 ra, u32 rb, u32 rt) = 0;
|
||||
virtual void FMS(u32 rc, u32 ra, u32 rb, u32 rt) = 0;
|
||||
|
||||
ADD_OPCODE(UNK,(const s32 code, const s32 opcode, const s32 gcode));
|
||||
virtual void UNK(u32 code, u32 opcode, u32 gcode) = 0;
|
||||
};
|
||||
|
||||
#undef START_OPCODES_GROUP
|
||||
#undef ADD_OPCODE
|
||||
#undef ADD_NULL_OPCODE
|
||||
#undef END_OPCODES_GROUP
|
||||
@ -97,7 +97,7 @@ CompilerELF::CompilerELF(wxWindow* parent)
|
||||
" addi r11, r0, sys_tty_write\n"
|
||||
" sc 2\n"
|
||||
" cmpi cr7, 0, r3, 0\n"
|
||||
" bc 0x04, 28, exit_err, 0, 0\n"
|
||||
" bc 0x04, 30, exit_err, 0, 0\n"
|
||||
"\n"
|
||||
"exit_ok:\n"
|
||||
" addi r3, r0, 0\n"
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
#include "stdafx.h"
|
||||
#include "InterpreterDisAsm.h"
|
||||
|
||||
static const int show_lines = 30;
|
||||
//static const int show_lines = 30;
|
||||
|
||||
u32 FixPc(const u32 pc)
|
||||
u32 InterpreterDisAsmFrame::CentrePc(const u32 pc) const
|
||||
{
|
||||
return pc - ((show_lines/2)*4);
|
||||
return pc - ((m_item_count / 2) * 4);
|
||||
}
|
||||
|
||||
InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu)
|
||||
@ -13,6 +13,7 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu)
|
||||
, ThreadBase(false, "DisAsmFrame Thread")
|
||||
, CPU(*cpu)
|
||||
, PC(0)
|
||||
, m_item_count(30)
|
||||
{
|
||||
if(CPU.IsSPU())
|
||||
{
|
||||
@ -64,8 +65,7 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu)
|
||||
Layout();
|
||||
|
||||
m_list->InsertColumn(0, "ASM");
|
||||
|
||||
for(uint i=0; i<show_lines; ++i)
|
||||
for(uint i=0; i<m_item_count; ++i)
|
||||
{
|
||||
m_list->InsertItem(m_list->GetItemCount(), wxEmptyString);
|
||||
}
|
||||
@ -77,7 +77,7 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu)
|
||||
Connect(m_btn_run->GetId(), wxEVT_COMMAND_BUTTON_CLICKED, wxCommandEventHandler(InterpreterDisAsmFrame::DoRun));
|
||||
Connect(m_btn_pause->GetId(), wxEVT_COMMAND_BUTTON_CLICKED, wxCommandEventHandler(InterpreterDisAsmFrame::DoPause));
|
||||
Connect(m_list->GetId(), wxEVT_COMMAND_LIST_ITEM_ACTIVATED, wxListEventHandler(InterpreterDisAsmFrame::DClick));
|
||||
//Connect(wxEVT_SIZE, wxSizeEventHandler(InterpreterDisAsmFrame::OnResize));
|
||||
Connect(wxEVT_SIZE, wxSizeEventHandler(InterpreterDisAsmFrame::OnResize));
|
||||
m_app_connector.Connect(m_list->GetId(), wxEVT_MOUSEWHEEL, wxMouseEventHandler(InterpreterDisAsmFrame::MouseWheel), (wxObject*)0, this);
|
||||
m_app_connector.Connect(wxEVT_KEY_DOWN, wxKeyEventHandler(InterpreterDisAsmFrame::OnKeyDown), (wxObject*)0, this);
|
||||
|
||||
@ -110,16 +110,50 @@ void InterpreterDisAsmFrame::OnKeyDown(wxKeyEvent& event)
|
||||
{
|
||||
switch(event.GetKeyCode())
|
||||
{
|
||||
case WXK_PAGEUP: ShowAddr( PC - (show_lines * 2) * 4 ); return;
|
||||
case WXK_PAGEUP: ShowAddr( PC - (m_item_count * 2) * 4 ); return;
|
||||
case WXK_PAGEDOWN: ShowAddr( PC ); return;
|
||||
case WXK_UP: ShowAddr( PC - (show_lines + 1) * 4 ); return;
|
||||
case WXK_DOWN: ShowAddr( PC - (show_lines - 1) * 4 ); return;
|
||||
case WXK_UP: ShowAddr( PC - (m_item_count + 1) * 4 ); return;
|
||||
case WXK_DOWN: ShowAddr( PC - (m_item_count - 1) * 4 ); return;
|
||||
}
|
||||
}
|
||||
|
||||
event.Skip();
|
||||
}
|
||||
|
||||
void InterpreterDisAsmFrame::OnResize(wxSizeEvent& event)
|
||||
{
|
||||
event.Skip();
|
||||
|
||||
if(0)
|
||||
{
|
||||
if(!m_list->GetItemCount())
|
||||
{
|
||||
m_list->InsertItem(m_list->GetItemCount(), wxEmptyString);
|
||||
}
|
||||
|
||||
int size = 0;
|
||||
m_list->DeleteAllItems();
|
||||
int item = 0;
|
||||
while(size < m_list->GetSize().GetHeight())
|
||||
{
|
||||
item = m_list->GetItemCount();
|
||||
m_list->InsertItem(item, wxEmptyString);
|
||||
wxRect rect;
|
||||
m_list->GetItemRect(item, rect);
|
||||
|
||||
size = rect.GetBottom();
|
||||
}
|
||||
|
||||
if(item)
|
||||
{
|
||||
m_list->DeleteItem(--item);
|
||||
}
|
||||
|
||||
m_item_count = item;
|
||||
ShowAddr(PC);
|
||||
}
|
||||
}
|
||||
|
||||
void InterpreterDisAsmFrame::DoUpdate()
|
||||
{
|
||||
Show_PC(wxCommandEvent());
|
||||
@ -130,7 +164,7 @@ void InterpreterDisAsmFrame::ShowAddr(const u64 addr)
|
||||
{
|
||||
PC = addr;
|
||||
m_list->Freeze();
|
||||
for(uint i=0; i<show_lines; ++i, PC += 4)
|
||||
for(uint i=0; i<m_item_count; ++i, PC += 4)
|
||||
{
|
||||
if(!Memory.IsGoodAddr(PC, 4))
|
||||
{
|
||||
@ -285,22 +319,25 @@ void InterpreterDisAsmFrame::Show_Val(wxCommandEvent& WXUNUSED(event))
|
||||
u64 pc = CPU.PC;
|
||||
sscanf(p_pc->GetLabel(), "%llx", &pc);
|
||||
remove_markedPC.AddCpy(Emu.GetMarkedPoints().AddCpy(pc));
|
||||
ShowAddr(FixPc(pc));
|
||||
ShowAddr(CentrePc(pc));
|
||||
}
|
||||
}
|
||||
|
||||
void InterpreterDisAsmFrame::Show_PC(wxCommandEvent& WXUNUSED(event))
|
||||
{
|
||||
ShowAddr(FixPc(CPU.PC));
|
||||
ShowAddr(CentrePc(CPU.PC));
|
||||
}
|
||||
|
||||
extern bool dump_enable;
|
||||
void InterpreterDisAsmFrame::DoRun(wxCommandEvent& WXUNUSED(event))
|
||||
{
|
||||
if(CPU.IsPaused()) CPU.Resume();
|
||||
if(Emu.IsPaused()) Emu.Resume();
|
||||
|
||||
CPU.Exec();
|
||||
if(!Emu.IsPaused())
|
||||
{
|
||||
CPU.Exec();
|
||||
}
|
||||
|
||||
//ThreadBase::Start();
|
||||
}
|
||||
|
||||
@ -319,7 +356,7 @@ void InterpreterDisAsmFrame::DClick(wxListEvent& event)
|
||||
long i = m_list->GetFirstSelected();
|
||||
if(i < 0) return;
|
||||
|
||||
const u64 start_pc = PC - show_lines*4;
|
||||
const u64 start_pc = PC - m_item_count*4;
|
||||
const u64 pc = start_pc + i*4;
|
||||
//ConLog.Write("pc=0x%llx", pc);
|
||||
|
||||
@ -341,7 +378,7 @@ void InterpreterDisAsmFrame::MouseWheel(wxMouseEvent& event)
|
||||
{
|
||||
const int value = (event.m_wheelRotation / event.m_wheelDelta);
|
||||
|
||||
ShowAddr( PC - (event.ControlDown() ? show_lines * (value + 1) : show_lines + value) * 4);
|
||||
ShowAddr( PC - (event.ControlDown() ? m_item_count * (value + 1) : m_item_count + value) * 4);
|
||||
|
||||
event.Skip();
|
||||
}
|
||||
|
||||
@ -19,6 +19,7 @@ class InterpreterDisAsmFrame
|
||||
wxButton* m_btn_run;
|
||||
wxButton* m_btn_pause;
|
||||
AppConnector m_app_connector;
|
||||
u32 m_item_count;
|
||||
|
||||
public:
|
||||
PPCThread& CPU;
|
||||
@ -27,7 +28,10 @@ public:
|
||||
InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu);
|
||||
~InterpreterDisAsmFrame();
|
||||
|
||||
u32 CentrePc(const u32 pc) const;
|
||||
|
||||
void OnKeyDown(wxKeyEvent& event);
|
||||
void OnResize(wxSizeEvent& event);
|
||||
void DoUpdate();
|
||||
void ShowAddr(const u64 addr);
|
||||
void WriteRegs();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user