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spu: Mask SRR0 at write

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This commit is contained in:
Eladash 2019-10-01 10:06:34 +03:00 committed by Ivan
parent 3455d76970
commit c2278fb879
4 changed files with 4 additions and 4 deletions
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2
rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
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@ -2369,6 +2369,7 @@ void spu_recompiler::WRCH(spu_opcode_t op)
case SPU_WrSRR0:
{
c->mov(*addr, SPU_OFF_32(gpr, op.rt, &v128::_u32, 3));
c->and_(*addr, 0x3fffc);
c->mov(SPU_OFF_32(srr0), *addr);
return;
}
@ -2712,7 +2713,6 @@ void spu_recompiler::BISL(spu_opcode_t op)
void spu_recompiler::IRET(spu_opcode_t op)
{
c->mov(*addr, SPU_OFF_32(srr0));
c->and_(*addr, 0x3fffc);
branch_indirect(op);
m_pos = -1;
}

2
rpcs3/Emu/Cell/SPUInterpreter.cpp
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@ -508,7 +508,7 @@ bool spu_interpreter::BISL(spu_thread& spu, spu_opcode_t op)
bool spu_interpreter::IRET(spu_thread& spu, spu_opcode_t op)
{
spu.pc = spu_branch_target(spu.srr0);
spu.pc = spu.srr0;
set_interrupt_status(spu, op);
return false;
}

2
rpcs3/Emu/Cell/SPURecompiler.cpp
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@ -5606,7 +5606,7 @@ public:
{
case SPU_WrSRR0:
{
m_ir->CreateStore(val.value, spu_ptr<u32>(&spu_thread::srr0));
m_ir->CreateStore(eval(val & 0x3fffc).value, spu_ptr<u32>(&spu_thread::srr0));
return;
}
case SPU_WrOutIntrMbox:

2
rpcs3/Emu/Cell/SPUThread.cpp
View File

@ -2436,7 +2436,7 @@ bool spu_thread::set_ch_value(u32 ch, u32 value)
{
case SPU_WrSRR0:
{
srr0 = value;
srr0 = value & 0x3fffc;
return true;
}