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https://github.com/RPCS3/rpcs3.git
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Stop including x86 intrinsics in other architectures
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parent
6718b0683e
commit
c572226b0d
@ -2806,6 +2806,7 @@ public:
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}
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}
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case SPU_RdDec:
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case SPU_RdDec:
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{
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{
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#if defined(ARCH_X64)
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if (utils::get_tsc_freq() && !(g_cfg.core.spu_loop_detection) && (g_cfg.core.clocks_scale == 100))
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if (utils::get_tsc_freq() && !(g_cfg.core.spu_loop_detection) && (g_cfg.core.clocks_scale == 100))
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{
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{
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const auto timestamp = m_ir->CreateLoad(get_type<u64>(), spu_ptr<u64>(&spu_thread::ch_dec_start_timestamp));
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const auto timestamp = m_ir->CreateLoad(get_type<u64>(), spu_ptr<u64>(&spu_thread::ch_dec_start_timestamp));
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@ -2823,7 +2824,7 @@ public:
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res.value = m_ir->CreateSub(dec_value, deltax);
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res.value = m_ir->CreateSub(dec_value, deltax);
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break;
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break;
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}
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}
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#endif
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res.value = call("spu_read_decrementer", &exec_read_dec, m_thread);
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res.value = call("spu_read_decrementer", &exec_read_dec, m_thread);
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break;
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break;
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}
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}
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@ -3511,6 +3512,7 @@ public:
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{
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{
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call("spu_get_events", &exec_get_events, m_thread, m_ir->getInt32(SPU_EVENT_TM));
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call("spu_get_events", &exec_get_events, m_thread, m_ir->getInt32(SPU_EVENT_TM));
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#if defined(ARCH_X64)
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if (utils::get_tsc_freq() && !(g_cfg.core.spu_loop_detection) && (g_cfg.core.clocks_scale == 100))
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if (utils::get_tsc_freq() && !(g_cfg.core.spu_loop_detection) && (g_cfg.core.clocks_scale == 100))
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{
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{
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const auto tsc = m_ir->CreateCall(get_intrinsic(llvm::Intrinsic::x86_rdtsc));
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const auto tsc = m_ir->CreateCall(get_intrinsic(llvm::Intrinsic::x86_rdtsc));
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@ -3520,6 +3522,7 @@ public:
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m_ir->CreateStore(tsctb, spu_ptr<u64>(&spu_thread::ch_dec_start_timestamp));
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m_ir->CreateStore(tsctb, spu_ptr<u64>(&spu_thread::ch_dec_start_timestamp));
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}
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}
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else
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else
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#endif
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{
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{
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m_ir->CreateStore(call("get_timebased_time", &get_timebased_time), spu_ptr<u64>(&spu_thread::ch_dec_start_timestamp));
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m_ir->CreateStore(call("get_timebased_time", &get_timebased_time), spu_ptr<u64>(&spu_thread::ch_dec_start_timestamp));
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}
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}
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