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Improved Zen chip detection
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kd-11
kd-11
parent
0e278d2299
commit
cbe0000d23
@ -2498,7 +2498,7 @@ u64 thread_ctrl::get_affinity_mask(thread_class group)
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if (const auto thread_count = std::thread::hardware_concurrency())
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{
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const u64 all_cores_mask = thread_count < 64 ? UINT64_MAX >> (64 - thread_count): UINT64_MAX;
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const u64 all_cores_mask = get_process_affinity_mask();
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switch (g_native_core_layout)
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{
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@ -2509,105 +2509,140 @@ u64 thread_ctrl::get_affinity_mask(thread_class group)
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}
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case native_core_arrangement::amd_ccx:
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{
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if (thread_count <= 8)
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{
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// Single CCX or not enough threads, do nothing
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return all_cores_mask;
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}
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u64 spu_mask, ppu_mask, rsx_mask;
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spu_mask = ppu_mask = rsx_mask = all_cores_mask; // Fallback, in case someone is messing with core config
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const auto system_id = utils::get_cpu_brand();
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if (thread_count >= 32)
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const auto family_id = utils::get_cpu_family();
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const auto model_id = utils::get_cpu_model();
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switch (family_id)
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{
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if (system_id.find("3950X") != umax)
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case 0x17: // Zen, Zen+, Zen2
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case 0x18: // Dhyana core (Zen)
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{
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// zen2
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// Ryzen 9 3950X
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// Assign threads 9-32
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if (model_id > 0x30)
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{
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// Zen2 (models 49, 96, 113, 144)
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// Much improved inter-CCX latency
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switch (thread_count)
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{
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case 128:
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case 64:
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case 48:
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case 32:
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// TR 3000 series, or R9 3950X, Assign threads 9-32
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ppu_mask = 0b11111111000000000000000000000000;
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spu_mask = 0b00000000111111110000000000000000;
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rsx_mask = 0b00000000000000001111111100000000;
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}
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else if (system_id.find("2970WX") != umax)
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{
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// zen+
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// Threadripper 2970WX
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// Assign threads 9-24
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ppu_mask = 0b000000111111000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b111111000000000000000000;
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}
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else
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{
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// zen(+)
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// Threadripper 1950X/2950X/2990WX
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// Assign threads 17-32
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ppu_mask = 0b00000000111111110000000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b11111111000000000000000000000000;
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}
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}
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else if (thread_count == 24)
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{
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if (system_id.find("3900X") != umax)
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{
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// zen2
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// Ryzen 9 3900X
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// Assign threads 7-22
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break;
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case 24:
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// 3900X, Assign threads 7-22
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ppu_mask = 0b111111000000000000000000;
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spu_mask = 0b000000111111000000000000;
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rsx_mask = 0b000000000000111111000000;
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}
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else
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{
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// zen(+)
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// Threadripper 1920X/2920X
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// Assign threads 13-24
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ppu_mask = 0b000000111111000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b111111000000000000000000;
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}
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}
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else if (thread_count == 16)
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{
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if (system_id.find("3700X") != umax || system_id.find("3800X") != umax)
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{
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// Ryzen 7 3700/3800 (x)
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// Assign threads 1-16
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break;
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case 16:
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// 3700, 3800 family, Assign threads 1-16
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ppu_mask = 0b0000000011110000;
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spu_mask = 0b1111111100000000;
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rsx_mask = 0b0000000000001111;
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}
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else
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{
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// zen(+)
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// Ryzen 7, Threadripper
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// Assign threads 3-16
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ppu_mask = 0b1111111100000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b0000000000111100;
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}
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}
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else if (thread_count == 12)
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{
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if (system_id.find("3600") != umax)
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{
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// zen2
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// R5 3600 (x)
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// Assign threads 1-12
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break;
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case 12:
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// 3600 family, Assign threads 1-12
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ppu_mask = 0b000000111000;
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spu_mask = 0b111111000000;
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rsx_mask = 0b000000000111;
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break;
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default:
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break;
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}
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}
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else
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{
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// zen(+)
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// R5 1600/2600 (x)
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// Assign threads 3-12
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// Zen, Zen+ (models 1, 8(+), 17, 24(+), 32)
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switch (thread_count)
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{
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case 64:
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// TR 2990WX, Assign threads 17-32
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ppu_mask = 0b00000000111111110000000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b11111111000000000000000000000000;
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break;
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case 48:
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// TR 2970WX, Assign threads 9-24
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ppu_mask = 0b000000111111000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b111111000000000000000000;
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break;
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case 32:
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// TR 2950X, TR 1950X, Assign threads 17-32
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ppu_mask = 0b00000000111111110000000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b11111111000000000000000000000000;
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break;
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case 24:
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// TR 1920X, 2920X, Assign threads 13-24
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ppu_mask = 0b000000111111000000000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b111111000000000000000000;
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break;
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case 16:
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// 1700, 1800, 2700, TR 1900X family
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ppu_mask = 0b1111111100000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b0000000000111100;
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break;
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case 12:
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// 1600, 2600 family, Assign threads 3-12
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ppu_mask = 0b111111000000;
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spu_mask = ppu_mask;
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rsx_mask = 0b000000111100;
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break;
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default:
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break;
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}
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}
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break;
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}
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case 0x19: // Zen3
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{
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// Single-CCX architecture, just disable SMT if wide enough
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// CCX now holds upto 16 threads
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// Lack of hw availability makes testing difficult
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switch (thread_count)
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{
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case 24:
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// 5900X, Use same scheduler as 3900X
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// Unverified on windows, may be worse than just disabling SMT and scheduler
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ppu_mask = 0b111111000000000000000000;
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spu_mask = 0b000000111111000000000000;
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rsx_mask = 0b000000000000111111000000;
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break;
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default:
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if (thread_count >= 16)
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{
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// Verified by more than one windows user on 16-thread CPU
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ppu_mask = spu_mask = rsx_mask = (0b10101010101010101010101010101010 & all_cores_mask);
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}
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else
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{
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// R5 & R3 don't seem to improve performance no matter how these are shuffled
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ppu_mask = spu_mask = rsx_mask = 0b11111111 & all_cores_mask;
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ppu_mask = spu_mask = rsx_mask = all_cores_mask;
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}
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break;
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}
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break;
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}
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default:
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{
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break;
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}
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}
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switch (group)
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@ -417,3 +417,46 @@ u32 utils::get_thread_count()
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return ::sysconf(_SC_NPROCESSORS_ONLN);
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#endif
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}
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u32 utils::get_cpu_family()
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{
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static const u32 g_value = []()
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{
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const u32 reg_value = get_cpuid(0x00000001, 0)[0]; // Processor feature info
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const u32 base_value = (reg_value >> 8) & 0xF;
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if (base_value == 0xF) [[likely]]
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{
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const u32 extended_value = (reg_value >> 20) & 0xFF;
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return base_value + extended_value;
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}
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else
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{
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return base_value;
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}
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}();
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return g_value;
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}
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u32 utils::get_cpu_model()
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{
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static const u32 g_value = []()
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{
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const u32 reg_value = get_cpuid(0x00000001, 0)[0]; // Processor feature info
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const u32 base_value = (reg_value >> 4) & 0xF;
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if (const auto base_family_id = (reg_value >> 8) & 0xF;
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base_family_id == 0x6 || base_family_id == 0xF) [[likely]]
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{
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const u32 extended_value = (reg_value >> 16) & 0xF;
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return base_value + (extended_value << 4);
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}
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else
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{
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return base_value;
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}
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}();
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return g_value;
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}
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@ -50,4 +50,8 @@ namespace utils
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u64 get_total_memory();
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u32 get_thread_count();
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u32 get_cpu_family();
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u32 get_cpu_model();
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}
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