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https://github.com/RPCS3/rpcs3.git
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SPU LLVM: fix perf regression
Bug in the analyser was created recently in #5882.
This commit is contained in:
Nekotekina
parent
69d2ea35b9
commit
d48dc29e55
@ -901,6 +901,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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m_block_info.set(entry_point / 4);
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m_entry_info.reset();
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m_entry_info.set(entry_point / 4);
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m_ret_info.reset();
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// Simple block entry workload list
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std::vector<u32> workload;
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@ -1151,6 +1152,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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if (sl && g_cfg.core.spu_block_size != spu_block_size_type::safe)
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{
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m_ret_info[pos / 4 + 1] = true;
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m_entry_info[pos / 4 + 1] = true;
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m_targets[pos].push_back(pos + 4);
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add_block(pos + 4);
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@ -1302,6 +1304,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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}
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else
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{
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m_ret_info[pos / 4 + 1] = true;
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m_entry_info[pos / 4 + 1] = true;
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m_targets[pos].push_back(pos + 4);
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add_block(pos + 4);
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@ -1336,6 +1339,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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if (g_cfg.core.spu_block_size != spu_block_size_type::safe)
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{
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m_ret_info[pos / 4 + 1] = true;
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m_entry_info[pos / 4 + 1] = true;
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m_targets[pos].push_back(pos + 4);
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add_block(pos + 4);
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@ -1763,6 +1767,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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{
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m_block_info[addr / 4] = false;
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m_entry_info[addr / 4] = false;
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m_ret_info[addr / 4] = false;
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m_preds.erase(addr);
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}
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}
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@ -1906,8 +1911,7 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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}
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}
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block.reg_origin[0] = 0x80000000;
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block.reg_origin_abs[0] = 0x80000000;
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block.analysis2 = false;
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}
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// Fixup block predeccessors to point to basic blocks, not last instructions
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@ -1936,7 +1940,10 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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if (m_entry_info[addr / 4])
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{
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// Register empty chunk
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m_chunks[addr];
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if (auto emp = m_chunks.try_emplace(addr); emp.second)
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{
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emp.first->second.joinable = m_ret_info[addr / 4];
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}
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}
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else
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{
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@ -2001,74 +2008,140 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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for (auto& bb : m_bbs)
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{
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auto& chunk = m_chunks.at(bb.second.chunk);
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chunk.bbs.push_back(bb.first);
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}
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workload.clear();
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workload.push_back(entry_point);
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// Fill register origin info
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// Fill workload adding targets
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for (u32 wi = 0; wi < workload.size(); wi++)
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{
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const u32 addr = workload[wi];
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auto& block = m_bbs.at(addr);
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if (block.reg_origin[0] == 0x80000000)
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{
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// Initialize entry point with default value: unknown origin (requires load)
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block.reg_origin.fill(0x40000);
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}
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if (block.reg_origin_abs[0] == 0x80000000)
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{
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block.reg_origin_abs.fill(0x40000);
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}
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const u32 addr = workload[wi];
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auto& block = m_bbs.at(addr);
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block.analysis2 = true;
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for (u32 target : block.targets)
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{
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auto& tb = m_bbs.at(target);
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// Target block is either queued for the first time, or on request
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bool enqueue = tb.reg_origin[0] == 0x80000000 || tb.reg_origin_abs[0] == 0x80000000;
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for (u32 i = 0; i < s_reg_max; i++)
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if (!tb.analysis2)
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{
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if (tb.chunk == block.chunk && tb.reg_origin[i] != -1)
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workload.push_back(target);
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}
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}
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block.reg_origin.fill(0x80000000);
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block.reg_origin_abs.fill(0x80000000);
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}
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// Fill register origin info
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while (true)
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{
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bool must_repeat = false;
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for (u32 wi = 0; wi < workload.size(); wi++)
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{
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const u32 addr = workload[wi];
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auto& block = m_bbs.at(addr);
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// Initialize entry point with default value: unknown origin (requires load)
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if (m_entry_info[addr / 4])
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{
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for (u32 i = 0; i < s_reg_max; i++)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin[i] == -1 ? addr : block.reg_origin[i];
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if (tb.reg_origin[i] != expected)
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{
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// Multiple origins merged (requires PHI node)
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tb.reg_origin[i] = -1;
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// Need to process this target block again in order to propagate -1
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enqueue = true;
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}
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}
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if (tb.chunk != block.chunk && target != addr + block.size * 4 && m_entry_info[target / 4])
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{
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// Skip call target completely
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continue;
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}
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if (tb.reg_origin_abs[i] != -1)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin_abs[i] == -1 ? addr : block.reg_origin_abs[i];
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if (tb.reg_origin_abs[i] != expected)
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{
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tb.reg_origin_abs[i] = -1;
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enqueue = true;
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}
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if (block.reg_origin[i] == 0x80000000)
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block.reg_origin[i] = 0x40000;
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}
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}
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if (enqueue)
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if (m_entry_info[addr / 4] && !m_chunks.at(addr).joinable)
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{
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workload.emplace_back(target);
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for (u32 i = 0; i < s_reg_max; i++)
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{
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if (block.reg_origin_abs[i] == 0x80000000)
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block.reg_origin_abs[i] = 0x40000;
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else if (block.reg_origin_abs[i] == -1)
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block.reg_origin_abs[i] = -2;
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}
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}
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for (u32 target : block.targets)
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{
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auto& tb = m_bbs.at(target);
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for (u32 i = 0; i < s_reg_max; i++)
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{
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if (tb.chunk == block.chunk && tb.reg_origin[i] != -1)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin[i] == -1 ? addr : block.reg_origin[i];
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if (tb.reg_origin[i] == 0x80000000)
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{
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tb.reg_origin[i] = expected;
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}
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else if (tb.reg_origin[i] != expected)
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{
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// Set -1 if multiple origins merged (requires PHI node)
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tb.reg_origin[i] = -1;
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must_repeat |= !tb.targets.empty();
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}
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}
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if (tb.chunk != block.chunk && m_entry_info[target / 4] && !m_chunks.at(target).joinable)
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{
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// Skip call targets completely
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continue;
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}
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if (tb.reg_origin_abs[i] != -2)
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{
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const u32 expected = block.reg_mod[i] || block.reg_origin_abs[i] >> 31 ? addr : block.reg_origin_abs[i];
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if (tb.reg_origin_abs[i] == 0x80000000)
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{
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tb.reg_origin_abs[i] = expected;
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}
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else if (tb.reg_origin_abs[i] != expected)
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{
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if (tb.reg_origin_abs[i] == 0x40000 || (!block.reg_mod[i] && (block.reg_origin_abs[i] == -2 || block.reg_origin_abs[i] == 0x40000)))
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{
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// Set -2: sticky value indicating possible external reg origin (0x40000)
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tb.reg_origin_abs[i] = -2;
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must_repeat |= !tb.targets.empty();
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}
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else if (tb.reg_origin_abs[i] != -1)
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{
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tb.reg_origin_abs[i] = -1;
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must_repeat |= !tb.targets.empty();
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}
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}
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}
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}
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}
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}
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if (!must_repeat)
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{
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break;
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}
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for (u32 wi = 0; wi < workload.size(); wi++)
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{
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const u32 addr = workload[wi];
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auto& block = m_bbs.at(addr);
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// Reset values for the next attempt (keep negative values)
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for (u32 i = 0; i < s_reg_max; i++)
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{
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if (block.reg_origin[i] <= 0x40000)
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block.reg_origin[i] = 0x80000000;
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if (block.reg_origin_abs[i] <= 0x40000)
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block.reg_origin_abs[i] = 0x80000000;
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}
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}
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}
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@ -2084,31 +2157,33 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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void spu_recompiler_base::dump(std::string& out)
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{
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for (u32 i = 0; i < 0x10000; i++)
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for (auto& bb : m_bbs)
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{
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if (m_block_info[i])
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if (m_block_info[bb.first / 4])
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{
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fmt::append(out, "A: [0x%05x] %s\n", i * 4, m_entry_info[i] ? "Entry" : "Block");
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fmt::append(out, "?: [0x%05x] %s\n", bb.first, m_entry_info[bb.first / 4] ? (m_ret_info[bb.first / 4] ? "Return" : "Entry") : "Block");
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if (auto found = m_chunks.find(bb.first); found != m_chunks.end())
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{
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if (found->second.joinable)
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fmt::append(out, "\tJoinable chunk.\n");
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else
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fmt::append(out, "\tNon-joinable chunk.\n");
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}
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for (u32 pred : bb.second.preds)
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{
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fmt::append(out, "\t<- 0x%05x\n", pred);
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}
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for (u32 target : bb.second.targets)
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{
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fmt::append(out, "\t-> 0x%05x\n", target);
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}
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}
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}
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for (auto&& pair : std::map<u32, std::basic_string<u32>>(m_targets.begin(), m_targets.end()))
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{
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fmt::append(out, "T: [0x%05x]\n", pair.first);
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for (u32 value : pair.second)
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else
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{
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fmt::append(out, "\t-> 0x%05x\n", value);
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}
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}
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for (auto&& pair : std::map<u32, std::basic_string<u32>>(m_preds.begin(), m_preds.end()))
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{
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fmt::append(out, "P: [0x%05x]\n", pair.first);
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for (u32 value : pair.second)
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{
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fmt::append(out, "\t<- 0x%05x\n", value);
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fmt::append(out, "?: [0x%05x] ?\n", bb.first);
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}
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}
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@ -2258,7 +2333,7 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
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{
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if (auto c = llvm::dyn_cast_or_null<llvm::Constant>(m_block->reg[i]))
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{
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if (m_bbs.at(addr).reg_origin_abs[i] != -1)
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if (m_bbs.at(addr).reg_origin_abs[i] < 0x40000)
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{
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regs[i] = c;
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}
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@ -3253,9 +3328,6 @@ public:
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{
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const u32 src = bb.reg_origin[i];
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//fs::file(m_spurt->get_cache_path() + "info.log", fs::write + fs::create + fs::append)
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// .write(fmt::format("0x%05x: $%u = 0x%05x\n", baddr, i, src >> 31 ? -1 : src));
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if (src == -1)
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{
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// TODO: type
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@ -3332,7 +3404,7 @@ public:
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LOG_ERROR(SPU, "[0x%05x] Value not found ($%u from 0x%05x)", baddr, i, src);
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}
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}
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else
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else if (baddr == m_entry)
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{
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// Passthrough constant from a different chunk (will be removed in future)
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m_block->reg[i] = m_finfo->reg[i];
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@ -224,6 +224,9 @@ protected:
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// List of function entry points and return points (set after BRSL, BRASL, BISL, BISLED)
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std::bitset<0x10000> m_entry_info;
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// Set after return points
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std::bitset<0x10000> m_ret_info;
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// Basic block information
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struct block_info
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{
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@ -233,6 +236,8 @@ protected:
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// Number of instructions
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u16 size = 0;
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u8 analysis2 : 1;
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// Bit mask of the registers modified in the block
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std::bitset<s_reg_max> reg_mod{};
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