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More SPU Instructions: Floating point arithmetic

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Implemented Floating/Double-floating arithmetic operations: Add,
Substract and Multiply: FA, FS, FM, DFA, DFS, DFM respectively.

* Fixed issue in the register editor: Wrong value displayed when reading
64 bit or 128 bit registers.

* Fixed issue in the register editor: Error when writing to 128 bit
registers.
This commit is contained in:
Alexandro Sánchez Bach 2013-09-23 01:50:16 +02:00
parent 9c6ae554fa
commit db7e68d308
3 changed files with 44 additions and 20 deletions
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22
rpcs3/Emu/Cell/PPUThread.h
View File

@ -759,14 +759,14 @@ public:
{
long reg_index;
reg.AfterFirst('[').RemoveLast().ToLong(&reg_index);
if (reg.StartsWith("GPR")) return wxString::Format("%016x", GPR[reg_index]);
if (reg.StartsWith("FPR")) return wxString::Format("%016x", FPR[reg_index]);
if (reg.StartsWith("VPR")) return wxString::Format("%032x", VPR[reg_index]);
if (reg.StartsWith("GPR")) return wxString::Format("%016llx", GPR[reg_index]);
if (reg.StartsWith("FPR")) return wxString::Format("%016llx", FPR[reg_index]);
if (reg.StartsWith("VPR")) return wxString::Format("%016llx%016llx", VPR[reg_index]._u64[1], VPR[reg_index]._u64[0]);
}
if (reg == "CR") return wxString::Format("%08x", CR);
if (reg == "LR") return wxString::Format("%016x", LR);
if (reg == "CTR") return wxString::Format("%016x", CTR);
if (reg == "XER") return wxString::Format("%016x", XER);
if (reg == "LR") return wxString::Format("%016llx", LR);
if (reg == "CTR") return wxString::Format("%016llx", CTR);
if (reg == "XER") return wxString::Format("%016llx", XER);
if (reg == "FPSCR") return wxString::Format("%08x", FPSCR);
return wxEmptyString;
}
@ -780,7 +780,7 @@ public:
if (reg.StartsWith("GPR") || (reg.StartsWith("FPR")))
{
unsigned long long reg_value;
if (!value.SubString(16,32).ToULongLong(&reg_value, 16)) return false;
if (!value.SubString(16,31).ToULongLong(&reg_value, 16)) return false;
if (reg.StartsWith("GPR")) GPR[reg_index] = (u64)reg_value;
if (reg.StartsWith("FPR")) FPR[reg_index] = (u64)reg_value;
return true;
@ -789,8 +789,8 @@ public:
{
unsigned long long reg_value0;
unsigned long long reg_value1;
if (!value.SubString(16,32).ToULongLong(&reg_value0, 16)) return false;
if (!value.SubString(0,16).ToULongLong(&reg_value1, 16)) return false;
if (!value.SubString(16,31).ToULongLong(&reg_value0, 16)) return false;
if (!value.SubString(0,15).ToULongLong(&reg_value1, 16)) return false;
VPR[reg_index]._u64[0] = (u64)reg_value0;
VPR[reg_index]._u64[1] = (u64)reg_value1;
return true;
@ -799,7 +799,7 @@ public:
if (reg == "LR" || reg == "CTR" || reg == "XER")
{
unsigned long long reg_value;
if (!value.SubString(16,32).ToULongLong(&reg_value, 16)) return false;
if (!value.SubString(16,31).ToULongLong(&reg_value, 16)) return false;
if (reg == "LR") LR = (u64)reg_value;
if (reg == "CTR") CTR = (u64)reg_value;
if (reg == "XER") XER.XER = (u64)reg_value;
@ -808,7 +808,7 @@ public:
if (reg == "CR" || reg == "FPSCR")
{
unsigned long reg_value;
if (!value.SubString(24,32).ToULong(&reg_value, 16)) return false;
if (!value.SubString(24,31).ToULong(&reg_value, 16)) return false;
if (reg == "CR") CR.CR = (u32)reg_value;
if (reg == "FPSCR") FPSCR.FPSCR = (u32)reg_value;
return true;

36
rpcs3/Emu/Cell/SPUInterpreter.h
View File

@ -682,15 +682,27 @@ private:
}
void FA(u32 rt, u32 ra, u32 rb)
{
UNIMPLEMENTED();
for (int w = 0; w < 4; w++)
{
float f = *(float*)&CPU.GPR[ra]._u32[w] + *(float*)&CPU.GPR[rb]._u32[w];
CPU.GPR[rt]._u32[w] = *(u32*)&f;
}
}
void FS(u32 rt, u32 ra, u32 rb)
{
UNIMPLEMENTED();
for (int w = 0; w < 4; w++)
{
float f = *(float*)&CPU.GPR[ra]._u32[w] - *(float*)&CPU.GPR[rb]._u32[w];
CPU.GPR[rt]._u32[w] = *(u32*)&f;
}
}
void FM(u32 rt, u32 ra, u32 rb)
{
UNIMPLEMENTED();
for (int w = 0; w < 4; w++)
{
float f = *(float*)&CPU.GPR[ra]._u32[w] * *(float*)&CPU.GPR[rb]._u32[w];
CPU.GPR[rt]._u32[w] = *(u32*)&f;
}
}
void CLGTH(u32 rt, u32 ra, u32 rb)
{
@ -712,15 +724,27 @@ private:
}
void DFA(u32 rt, u32 ra, u32 rb)
{
UNIMPLEMENTED();
for (int w = 0; w < 2; w++)
{
double d = *(double*)&CPU.GPR[ra]._u64[w] + *(double*)&CPU.GPR[rb]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
}
void DFS(u32 rt, u32 ra, u32 rb)
{
UNIMPLEMENTED();
for (int w = 0; w < 2; w++)
{
double d = *(double*)&CPU.GPR[ra]._u64[w] - *(double*)&CPU.GPR[rb]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
}
void DFM(u32 rt, u32 ra, u32 rb)
{
UNIMPLEMENTED();
for (int w = 0; w < 2; w++)
{
double d = *(double*)&CPU.GPR[ra]._u64[w] * *(double*)&CPU.GPR[rb]._u64[w];
CPU.GPR[rt]._u64[w] = *(u64*)&d;
}
}
void CLGTB(u32 rt, u32 ra, u32 rb)
{

6
rpcs3/Emu/Cell/SPUThread.h
View File

@ -255,7 +255,7 @@ public:
{
long reg_index;
reg.AfterFirst('[').RemoveLast().ToLong(&reg_index);
if (reg.StartsWith("GPR")) return wxString::Format("%032x", GPR[reg_index]);
if (reg.StartsWith("GPR")) return wxString::Format("%016llx%016llx", GPR[reg_index]._u64[1], GPR[reg_index]._u64[0]);
}
return wxEmptyString;
}
@ -270,8 +270,8 @@ public:
{
unsigned long long reg_value0;
unsigned long long reg_value1;
if (!value.SubString(16,32).ToULongLong(&reg_value0, 16)) return false;
if (!value.SubString(0,16).ToULongLong(&reg_value1, 16)) return false;
if (!value.SubString(16,31).ToULongLong(&reg_value0, 16)) return false;
if (!value.SubString(0,15).ToULongLong(&reg_value1, 16)) return false;
GPR[reg_index]._u64[0] = (u64)reg_value0;
GPR[reg_index]._u64[1] = (u64)reg_value1;
return true;