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PPU LLVM/RawSPU: Fixup MMIO crossing-out

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Eladash 2023-08-04 20:28:41 +03:00 committed by Elad Ashkenazi
parent 6672499dde
commit e25936c1f1
1 changed files with 15 additions and 3 deletions
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18
rpcs3/Emu/Cell/PPUTranslator.cpp
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@ -3617,11 +3617,11 @@ void PPUTranslator::LWZ(ppu_opcode_t op)
m_may_be_mmio &= (op.ra != 1u && op.ra != 13u); // Stack register and TLS address register are unlikely to be used in MMIO address calculation
m_may_be_mmio &= op.simm16 == 0 || spu_thread::test_is_problem_state_register_offset(op.uimm16, true, false); // Either exact MMIO address or MMIO base with completing s16 address offset
if (m_may_be_mmio && !op.simm16)
if (m_may_be_mmio)
{
struct instructions_data
{
be_t<u32> insts[2];
be_t<u32> insts[3];
};
// Quick invalidation: expect exact MMIO address, so if the register is being reused with different offset than it's likely not MMIO
@ -3637,6 +3637,12 @@ void PPUTranslator::LWZ(ppu_opcode_t op)
continue;
}
if (op.simm16 && spu_thread::test_is_problem_state_register_offset(test_op.uimm16, true, false))
{
// Found register reuse with different MMIO offset
continue;
}
switch (g_ppu_itype.decode(inst))
{
case ppu_itype::LWZ:
@ -3714,7 +3720,7 @@ void PPUTranslator::STW(ppu_opcode_t op)
m_may_be_mmio &= (op.ra != 1u && op.ra != 13u); // Stack register and TLS address register are unlikely to be used in MMIO address calculation
m_may_be_mmio &= op.simm16 == 0 || spu_thread::test_is_problem_state_register_offset(op.uimm16, false, true); // Either exact MMIO address or MMIO base with completing s16 address offset
if (m_may_be_mmio && !op.simm16)
if (m_may_be_mmio)
{
struct instructions_data
{
@ -3734,6 +3740,12 @@ void PPUTranslator::STW(ppu_opcode_t op)
continue;
}
if (op.simm16 && spu_thread::test_is_problem_state_register_offset(test_op.uimm16, false, true))
{
// Found register reuse with different MMIO offset
continue;
}
switch (g_ppu_itype.decode(inst))
{
case ppu_itype::LWZ: