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https://github.com/RPCS3/rpcs3.git
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rsx: Rework loop interrupts a bit
- Reset backend interrupt in core handler - Separate memory config interrupt from regular backend interrupt
This commit is contained in:
parent
d0dc095c84
commit
e368453751
@ -967,6 +967,7 @@ bool GLGSRender::on_access_violation(u32 address, bool is_writing)
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{
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{
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auto &task = post_flush_request(address, result);
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auto &task = post_flush_request(address, result);
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m_graphics_state |= ~rsx::pipeline_state::backend_interrupt;
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vm::temporary_unlock();
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vm::temporary_unlock();
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task.producer_wait();
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task.producer_wait();
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}
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}
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@ -767,7 +767,7 @@ namespace rsx
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// This avoids expensive calls to check timestamps which involves reading some values from TLS storage on windows.
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// This avoids expensive calls to check timestamps which involves reading some values from TLS storage on windows.
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// If something is going on in the backend that requires an update, set the interrupt bit explicitly.
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// If something is going on in the backend that requires an update, set the interrupt bit explicitly.
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if ((m_cycles_counter++ & 63) == 0 ||
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if ((m_cycles_counter++ & 63) == 0 ||
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m_graphics_state & (rsx::pipeline_state::backend_interrupt_bits))
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m_graphics_state & rsx::pipeline_state::backend_interrupt_bits)
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{
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{
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// Execute backend-local tasks first
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// Execute backend-local tasks first
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do_local_task(performance_counters.state);
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do_local_task(performance_counters.state);
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@ -1049,6 +1049,8 @@ namespace rsx
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void thread::do_local_task(FIFO_state state)
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void thread::do_local_task(FIFO_state state)
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{
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{
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m_graphics_state &= ~rsx::pipeline_state::backend_interrupt;
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if (async_flip_requested & flip_request::emu_requested)
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if (async_flip_requested & flip_request::emu_requested)
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{
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{
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// NOTE: This has to be executed immediately
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// NOTE: This has to be executed immediately
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@ -2960,13 +2962,15 @@ namespace rsx
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m_invalidated_memory_range = unmap_range;
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m_invalidated_memory_range = unmap_range;
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}
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}
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m_graphics_state |= rsx::pipeline_state::backend_interrupt;
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m_graphics_state |= rsx::pipeline_state::memory_config_interrupt;
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}
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}
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}
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}
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// NOTE: m_mtx_task lock must be acquired before calling this method
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// NOTE: m_mtx_task lock must be acquired before calling this method
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void thread::handle_invalidated_memory_range()
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void thread::handle_invalidated_memory_range()
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{
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{
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m_graphics_state &= ~rsx::pipeline_state::memory_config_interrupt;
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if (!m_invalidated_memory_range.valid())
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if (!m_invalidated_memory_range.valid())
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return;
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return;
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@ -133,13 +133,14 @@ namespace rsx
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push_buffer_arrays_dirty = 0x20000, // Push buffers have data written to them (immediate mode vertex buffers)
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push_buffer_arrays_dirty = 0x20000, // Push buffers have data written to them (immediate mode vertex buffers)
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backend_interrupt = 0x80000000, // Backend interrupt, must serve immediately
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backend_interrupt = 0x80000000, // Backend interrupt, must serve immediately
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memory_config_interrupt = 0x40000000, // Memory configuration changed
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fragment_program_dirty = fragment_program_ucode_dirty | fragment_program_state_dirty,
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fragment_program_dirty = fragment_program_ucode_dirty | fragment_program_state_dirty,
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vertex_program_dirty = vertex_program_ucode_dirty | vertex_program_state_dirty,
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vertex_program_dirty = vertex_program_ucode_dirty | vertex_program_state_dirty,
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invalidate_pipeline_bits = fragment_program_dirty | vertex_program_dirty,
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invalidate_pipeline_bits = fragment_program_dirty | vertex_program_dirty,
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invalidate_zclip_bits = vertex_state_dirty | zclip_config_state_dirty,
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invalidate_zclip_bits = vertex_state_dirty | zclip_config_state_dirty,
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memory_barrier_bits = framebuffer_reads_dirty,
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memory_barrier_bits = framebuffer_reads_dirty,
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backend_interrupt_bits = memory_barrier_bits | backend_interrupt,
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backend_interrupt_bits = memory_barrier_bits | memory_config_interrupt | backend_interrupt,
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all_dirty = ~0u
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all_dirty = ~0u
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};
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};
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@ -825,6 +825,7 @@ bool VKGSRender::on_access_violation(u32 address, bool is_writing)
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std::lock_guard lock(m_flush_queue_mutex);
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std::lock_guard lock(m_flush_queue_mutex);
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m_flush_requests.post(false);
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m_flush_requests.post(false);
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m_graphics_state |= rsx::pipeline_state::backend_interrupt;
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has_queue_ref = true;
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has_queue_ref = true;
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}
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}
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else
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else
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@ -1645,9 +1646,6 @@ void VKGSRender::sync_hint(rsx::FIFO_hint hint, rsx::reports::sync_hint_payload_
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void VKGSRender::do_local_task(rsx::FIFO_state state)
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void VKGSRender::do_local_task(rsx::FIFO_state state)
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{
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{
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// Clear interrupt bit if set
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m_graphics_state &= ~rsx::pipeline_state::backend_interrupt;
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if (m_queue_status & flush_queue_state::deadlock)
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if (m_queue_status & flush_queue_state::deadlock)
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{
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{
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// Clear offloader deadlock
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// Clear offloader deadlock
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