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STBUX implemented

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Missed PPU opcode + replaced some non-unicode non-ASCII characters in
PPPInstrTable.h
This commit is contained in:
Nekotekina 2013-12-14 04:15:20 +04:00
parent ee137323aa
commit eed6a7ffe3
4 changed files with 16 additions and 3 deletions
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4
rpcs3/Emu/Cell/PPUDisAsm.h
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@ -1399,6 +1399,10 @@ private:
{
DisAsm_R3("stdux", rs, ra, rb);
}
void STBUX(u32 rs, u32 ra, u32 rb)
{
DisAsm_R3("stbux", rs, ra, rb);
}
void STVEWX(u32 vs, u32 ra, u32 rb)
{
DisAsm_V1_R2("stvewx", vs, ra, rb);

7
rpcs3/Emu/Cell/PPUInstrTable.h
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@ -78,7 +78,7 @@ namespace PPU_instr
static CodeField<11, 15> BI;
//Immediate field specifying a 14-bit signed two's complement branch displacement that is concatenated on the
//right with ‘00’ and sign-extended to 64 bits.
//right with '00' and sign-extended to 64 bits.
static CodeFieldSigned<16, 31> BD(FIELD_BRANCH);
//
@ -179,9 +179,9 @@ namespace PPU_instr
Record bit.
0 Does not update the condition register (CR).
1 Updates the CR to reflect the result of the operation.
For integer instructions, CR bits [0–2] are set to reflect the result as a signed quantity and CR bit [3]
For integer instructions, CR bits [0-2] are set to reflect the result as a signed quantity and CR bit [3]
receives a copy of the summary overflow bit, XER[SO]. The result as an unsigned quantity or a bit
string can be deduced from the EQ bit. For floating-point instructions, CR bits [4–7] are set to reflect
string can be deduced from the EQ bit. For floating-point instructions, CR bits [4-7] are set to reflect
floating-point exception, floating-point enabled exception, floating-point invalid operation exception,
and floating-point overflow exception.
*/
@ -482,6 +482,7 @@ namespace PPU_instr
/*0x097*/bind_instr(g1f_list, STWX, RS, RA, RB);
/*0x0a7*/bind_instr(g1f_list, STVEHX, VS, RA, RB);
/*0x0b5*/bind_instr(g1f_list, STDUX, RS, RA, RB);
/*0x0f7*/bind_instr(g1f_list, STBUX, RS, RA, RB);
/*0x0c7*/bind_instr(g1f_list, STVEWX, VS, RA, RB);
/*0x0ca*/bind_instr(g1f_list, ADDZE, RD, RA, OE, RC);
/*0x0d6*/bind_instr(g1f_list, STDCX_, RS, RA, RB);

6
rpcs3/Emu/Cell/PPUInterpreter.h
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@ -2650,6 +2650,12 @@ private:
Memory.Write64(addr, CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void STBUX(u32 rs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write8(addr, CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void STVEWX(u32 vs, u32 ra, u32 rb)
{
const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;

2
rpcs3/Emu/Cell/PPUOpcodes.h
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@ -297,6 +297,7 @@ namespace PPU_opcodes
STWX = 0x097,
STVEHX = 0x0a7, //Store Vector Element Halfword Indexed
STDUX = 0x0b5,
STBUX = 0x0f7,
STVEWX = 0x0c7, //Store Vector Element Word Indexed
ADDZE = 0x0ca,
STDCX_ = 0x0d6,
@ -678,6 +679,7 @@ public:
virtual void STWX(u32 rs, u32 ra, u32 rb) = 0;
virtual void STVEHX(u32 vs, u32 ra, u32 rb) = 0;
virtual void STDUX(u32 rs, u32 ra, u32 rb) = 0;
virtual void STBUX(u32 rs, u32 ra, u32 rb) = 0;
virtual void STVEWX(u32 vs, u32 ra, u32 rb) = 0;
virtual void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) = 0;
virtual void STDCX_(u32 rs, u32 ra, u32 rb) = 0;