From 5a1ce28105cd3154db2687b53e0f01d2b6b255c2 Mon Sep 17 00:00:00 2001 From: Peter Tissen Date: Wed, 19 Mar 2014 23:40:49 +0100 Subject: [PATCH 1/2] fix carry errors --- rpcs3/Emu/Cell/PPUInterpreter.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h index c507b1aaa5..9c22befd5a 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter.h +++ b/rpcs3/Emu/Cell/PPUInterpreter.h @@ -2738,7 +2738,7 @@ private: { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = ~RA + CPU.XER.CA; - CPU.XER.CA = (0x8000000000000000 & RA) && (0x8000000000000000 & CPU.GPR[rd]);//RA <= 0ull; + CPU.XER.CA = (~RA + CPU.XER.CA > ~0x0) | ((RA == 0) & CPU.XER.CA); if (oe) ConLog.Warning("subfzeo"); if (rc) CPU.UpdateCR0(CPU.GPR[rd]); } @@ -2771,7 +2771,7 @@ private: { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = ~RA + CPU.XER.CA + 0xFFFFFFFFFFFFFFFF; - CPU.XER.CA = !(0x8000000000000000 & RA) && !(0x8000000000000000 & CPU.GPR[rd]); + CPU.XER.CA = (~RA + CPU.XER.CA > ~0xFFFFFFFFFFFFFFFF) | ((RA == 0) & CPU.XER.CA); if (oe) ConLog.Warning("subfmeo"); if (rc) CPU.UpdateCR0(CPU.GPR[rd]); } From 87e016bdf039fb222c82c118f340d010983e9534 Mon Sep 17 00:00:00 2001 From: Nekotekina Date: Wed, 19 Mar 2014 18:47:28 +0400 Subject: [PATCH 2/2] RLWIMI, RLWINM and RLWNM fixed --- rpcs3/Emu/Cell/PPUInterpreter.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h index 9c22befd5a..de17f60470 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter.h +++ b/rpcs3/Emu/Cell/PPUInterpreter.h @@ -46,8 +46,8 @@ u64 rotl64(const u64 x, const u8 n) { return (x << n) | (x >> (64 - n)); } u64 rotr64(const u64 x, const u8 n) { return (x >> n) | (x << (64 - n)); } */ -#define rotl32 _rotl -#define rotr32 _rotr +#define rotl32(x, n) _rotl64((u64)(u32)x | ((u64)(u32)x << 32), n) +#define rotr32(x, n) _rotr64((u64)(u32)x | ((u64)(u32)x << 32), n) #define rotl64 _rotl64 #define rotr64 _rotr64 @@ -2177,7 +2177,7 @@ private: } void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { - const u32 mask = rotate_mask[32 + mb][32 + me]; + const u64 mask = rotate_mask[32 + mb][32 + me]; CPU.GPR[ra] = (CPU.GPR[ra] & ~mask) | (rotl32(CPU.GPR[rs], sh) & mask); if(rc) CPU.UpdateCR0(CPU.GPR[ra]); }