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rsx: Properly decode packed renders from the type flag
- Seems to occupy bits [8-9]
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7c379432dd
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@ -1053,62 +1053,23 @@ namespace rsx
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fmt::throw_exception("Unknown framebuffer context 0x%x" HERE, (u32)context);
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}
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auto check_swizzled_render = [&]()
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{
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// Packed rasterization with optimal memory layout
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// Pitch has to be packed for all active render targets, i.e 64
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// Formats also seemingly need matching depth and color pitch if both are active
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if (color_buffer_unused)
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{
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// Check only depth
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return (layout.zeta_pitch == 64);
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}
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else if (depth_buffer_unused)
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{
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// Check only color
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for (const auto& index : rsx::utility::get_rtt_indexes(layout.target))
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{
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if (layout.color_pitch[index] != 64)
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{
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return false;
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}
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}
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return true;
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}
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if (depth_texel_size != color_texel_size)
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{
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// Both depth and color exist, but pixel size differs
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return false;
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}
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else
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{
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// Qualifies, but only if all the pitch values are disabled (64)
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// Both depth and color are assumed to exist in this case, unless proven otherwise
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if (layout.zeta_pitch != 64)
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{
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return false;
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}
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for (const auto& index : rsx::utility::get_rtt_indexes(layout.target))
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{
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if (layout.color_pitch[index] != 64)
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{
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return false;
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}
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}
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return true;
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}
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};
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// Swizzled render does tight packing of bytes
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const bool packed_render = check_swizzled_render();
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bool packed_render = false;
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u32 minimum_color_pitch = 64u;
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u32 minimum_zeta_pitch = 64u;
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switch (const auto mode = rsx::method_registers.surface_type())
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{
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default:
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LOG_ERROR(RSX, "Unknown raster mode 0x%x", (u32)mode);
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[[fallthrough]];
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case rsx::surface_raster_type::linear:
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break;
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case rsx::surface_raster_type::swizzle:
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packed_render = true;
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break;
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};
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if (!packed_render)
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{
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// Well, this is a write operation either way (clearing or drawing)
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@ -61,6 +61,12 @@ namespace rsx
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surface_depth_format to_surface_depth_format(u8 in);
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enum class surface_raster_type : u8
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{
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linear = 1,
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swizzle = 2,
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};
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enum class surface_antialiasing : u8
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{
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center_1_sample,
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@ -3530,6 +3530,7 @@ struct registers_decoder<NV4097_SET_SURFACE_FORMAT>
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u32 raw_value;
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bitfield_decoder_t<0, 5> color_fmt;
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bitfield_decoder_t<5, 3> depth_fmt;
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bitfield_decoder_t<8, 4> type;
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bitfield_decoder_t<12, 4> antialias;
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bitfield_decoder_t<16, 8> log2width;
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bitfield_decoder_t<24, 8> log2height;
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@ -3547,6 +3548,11 @@ struct registers_decoder<NV4097_SET_SURFACE_FORMAT>
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return to_surface_depth_format(m_data.depth_fmt);
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}
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surface_raster_type type() const
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{
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return static_cast<surface_raster_type>(u8(m_data.type));
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}
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surface_antialiasing antialias() const
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{
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return to_surface_antialiasing(m_data.antialias);
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@ -1243,6 +1243,11 @@ namespace rsx
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return decode<NV4097_SET_SURFACE_FORMAT>().depth_fmt();
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}
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surface_raster_type surface_type() const
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{
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return decode<NV4097_SET_SURFACE_FORMAT>().type();
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}
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surface_antialiasing surface_antialias() const
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{
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return decode<NV4097_SET_SURFACE_FORMAT>().antialias();
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