pmret/binutils-papermario
1
0
Fork 0
mirror of https://github.com/pmret/binutils-papermario.git synced 2024-10-18 19:12:35 +02:00
Code Issues Packages Projects Releases Wiki Activity
d5e06ff2a7
binutils-papermario/gas/doc/as.info-5
Ethan Roseman 772b37839e Initial commit of GNU Binutils 2.9.1
2020-09-20 20:52:02 -04:00

1271 lines
42 KiB
Plaintext
Raw Blame History

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

This is Info file as.info, produced by Makeinfo version 1.68 from the
input file as.texinfo.
START-INFO-DIR-ENTRY
* As: (as). The GNU assembler.
END-INFO-DIR-ENTRY
This file documents the GNU Assembler "as".
Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software
Foundation, Inc.
Permission is granted to make and distribute verbatim copies of this
manual provided the copyright notice and this permission notice are
preserved on all copies.
Permission is granted to copy and distribute modified versions of
this manual under the conditions for verbatim copying, provided that
the entire resulting derived work is distributed under the terms of a
permission notice identical to this one.
Permission is granted to copy and distribute translations of this
manual into another language, under the above conditions for modified
versions.

File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960
Compare-and-Branch
..................
The 960 architectures provide combined Compare-and-Branch
instructions that permit you to store the branch target in the lower 13
bits of the instruction word itself. However, if you specify a branch
target far enough away that its address won't fit in 13 bits, the
assembler can either issue an error, or convert your Compare-and-Branch
instruction into separate instructions to do the compare and the branch.
Whether `as' gives an error or expands the instruction depends on
two choices you can make: whether you use the `-no-relax' option, and
whether you use a "Compare and Branch" instruction or a "Compare and
Jump" instruction. The "Jump" instructions are *always* expanded if
necessary; the "Branch" instructions are expanded when necessary
*unless* you specify `-no-relax'--in which case `as' gives an error
instead.
These are the Compare-and-Branch instructions, their "Jump" variants,
and the instruction pairs they may expand into:
Compare and
Branch Jump Expanded to
------ ------ ------------
bbc chkbit; bno
bbs chkbit; bo
cmpibe cmpije cmpi; be
cmpibg cmpijg cmpi; bg
cmpibge cmpijge cmpi; bge
cmpibl cmpijl cmpi; bl
cmpible cmpijle cmpi; ble
cmpibno cmpijno cmpi; bno
cmpibne cmpijne cmpi; bne
cmpibo cmpijo cmpi; bo
cmpobe cmpoje cmpo; be
cmpobg cmpojg cmpo; bg
cmpobge cmpojge cmpo; bge
cmpobl cmpojl cmpo; bl
cmpoble cmpojle cmpo; ble
cmpobne cmpojne cmpo; bne

File: as.info, Node: M68K-Dependent, Next: MIPS-Dependent, Prev: i960-Dependent, Up: Machine Dependencies
M680x0 Dependent Features
=========================
* Menu:
* M68K-Opts:: M680x0 Options
* M68K-Syntax:: Syntax
* M68K-Moto-Syntax:: Motorola Syntax
* M68K-Float:: Floating Point
* M68K-Directives:: 680x0 Machine Directives
* M68K-opcodes:: Opcodes

File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent
M680x0 Options
--------------
The Motorola 680x0 version of `as' has a few machine dependent
options.
You can use the `-l' option to shorten the size of references to
undefined symbols. If you do not use the `-l' option, references to
undefined symbols are wide enough for a full `long' (32 bits). (Since
`as' cannot know where these symbols end up, `as' can only allocate
space for the linker to fill in later. Since `as' does not know how
far away these symbols are, it allocates as much space as it can.) If
you use this option, the references are only one word wide (16 bits).
This may be useful if you want the object file to be as small as
possible, and you know that the relevant symbols are always less than
17 bits away.
For some configurations, especially those where the compiler normally
does not prepend an underscore to the names of user variables, the
assembler requires a `%' before any use of a register name. This is
intended to let the assembler distinguish between C variables and
functions named `a0' through `a7', and so on. The `%' is always
accepted, but is not required for certain configurations, notably
`sun3'. The `--register-prefix-optional' option may be used to permit
omitting the `%' even for configurations for which it is normally
required. If this is done, it will generally be impossible to refer to
C variables and functions with the same names as register names.
Normally the character `|' is treated as a comment character, which
means that it can not be used in expressions. The `--bitwise-or'
option turns `|' into a normal character. In this mode, you must
either use C style comments, or start comments with a `#' character at
the beginning of a line.
If you use an addressing mode with a base register without specifying
the size, `as' will normally use the full 32 bit value. For example,
the addressing mode `%a0@(%d0)' is equivalent to `%a0@(%d0:l)'. You
may use the `--base-size-default-16' option to tell `as' to default to
using the 16 bit value. In this case, `%a0@(%d0)' is equivalent to
`%a0@(%d0:w)'. You may use the `--base-size-default-32' option to
restore the default behaviour.
If you use an addressing mode with a displacement, and the value of
the displacement is not known, `as' will normally assume that the value
is 32 bits. For example, if the symbol `disp' has not been defined,
`as' will assemble the addressing mode `%a0@(disp,%d0)' as though
`disp' is a 32 bit value. You may use the `--disp-size-default-16'
option to tell `as' to instead assume that the displacement is 16 bits.
In this case, `as' will assemble `%a0@(disp,%d0)' as though `disp' is
a 16 bit value. You may use the `--disp-size-default-32' option to
restore the default behaviour.
`as' can assemble code for several different members of the Motorola
680x0 family. The default depends upon how `as' was configured when it
was built; normally, the default is to assemble code for the 68020
microprocessor. The following options may be used to change the
default. These options control which instructions and addressing modes
are permitted. The members of the 680x0 family are very similar. For
detailed information about the differences, see the Motorola manuals.
`-m68000'
`-m68ec000'
`-m68hc000'
`-m68hc001'
`-m68008'
`-m68302'
`-m68306'
`-m68307'
`-m68322'
`-m68356'
Assemble for the 68000. `-m68008', `-m68302', and so on are
synonyms for `-m68000', since the chips are the same from the
point of view of the assembler.
`-m68010'
Assemble for the 68010.
`-m68020'
`-m68ec020'
Assemble for the 68020. This is normally the default.
`-m68030'
`-m68ec030'
Assemble for the 68030.
`-m68040'
`-m68ec040'
Assemble for the 68040.
`-m68060'
`-m68ec060'
Assemble for the 68060.
`-mcpu32'
`-m68330'
`-m68331'
`-m68332'
`-m68333'
`-m68334'
`-m68336'
`-m68340'
`-m68341'
`-m68349'
`-m68360'
Assemble for the CPU32 family of chips.
`-m5200'
Assemble for the ColdFire family of chips.
`-m68881'
`-m68882'
Assemble 68881 floating point instructions. This is the default
for the 68020, 68030, and the CPU32. The 68040 and 68060 always
support floating point instructions.
`-mno-68881'
Do not assemble 68881 floating point instructions. This is the
default for 68000 and the 68010. The 68040 and 68060 always
support floating point instructions, even if this option is used.
`-m68851'
Assemble 68851 MMU instructions. This is the default for the
68020, 68030, and 68060. The 68040 accepts a somewhat different
set of MMU instructions; `-m68851' and `-m68040' should not be used
together.
`-mno-68851'
Do not assemble 68851 MMU instructions. This is the default for
the 68000, 68010, and the CPU32. The 68040 accepts a somewhat
different set of MMU instructions.

File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent
Syntax
------
This syntax for the Motorola 680x0 was developed at MIT.
The 680x0 version of `as' uses instructions names and syntax
compatible with the Sun assembler. Intervening periods are ignored;
for example, `movl' is equivalent to `mov.l'.
In the following table APC stands for any of the address registers
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
relative to the program counter (`%zpc'), a suppressed address register
(`%za0' through `%za7'), or it may be omitted entirely. The use of
SIZE means one of `w' or `l', and it may be omitted, along with the
leading colon, unless a scale is also specified. The use of SCALE
means one of `1', `2', `4', or `8', and it may always be omitted along
with the leading colon.
The following addressing modes are understood:
"Immediate"
`#NUMBER'
"Data Register"
`%d0' through `%d7'
"Address Register"
`%a0' through `%a7'
`%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is
also known as `%fp', the Frame Pointer.
"Address Register Indirect"
`%a0@' through `%a7@'
"Address Register Postincrement"
`%a0@+' through `%a7@+'
"Address Register Predecrement"
`%a0@-' through `%a7@-'
"Indirect Plus Offset"
`APC@(NUMBER)'
"Index"
`APC@(NUMBER,REGISTER:SIZE:SCALE)'
The NUMBER may be omitted.
"Postindex"
`APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
The ONUMBER or the REGISTER, but not both, may be omitted.
"Preindex"
`APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
The NUMBER may be omitted. Omitting the REGISTER produces the
Postindex addressing mode.
"Absolute"
`SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.

File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent
Motorola Syntax
---------------
The standard Motorola syntax for this chip differs from the syntax
already discussed (*note Syntax: M68K-Syntax.). `as' can accept
Motorola syntax for operands, even if MIT syntax is used for other
operands in the same instruction. The two kinds of syntax are fully
compatible.
In the following table APC stands for any of the address registers
(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
relative to the program counter (`%zpc'), or a suppressed address
register (`%za0' through `%za7'). The use of SIZE means one of `w' or
`l', and it may always be omitted along with the leading dot. The use
of SCALE means one of `1', `2', `4', or `8', and it may always be
omitted along with the leading asterisk.
The following additional addressing modes are understood:
"Address Register Indirect"
`(%a0)' through `(%a7)'
`%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is
also known as `%fp', the Frame Pointer.
"Address Register Postincrement"
`(%a0)+' through `(%a7)+'
"Address Register Predecrement"
`-(%a0)' through `-(%a7)'
"Indirect Plus Offset"
`NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.
The NUMBER may also appear within the parentheses, as in
`(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted
(with an address register, omitting the NUMBER produces Address
Register Indirect mode).
"Index"
`NUMBER(APC,REGISTER.SIZE*SCALE)'
The NUMBER may be omitted, or it may appear within the
parentheses. The APC may be omitted. The REGISTER and the APC
may appear in either order. If both APC and REGISTER are address
registers, and the SIZE and SCALE are omitted, then the first
register is taken as the base register, and the second as the
index register.
"Postindex"
`([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
The ONUMBER, or the REGISTER, or both, may be omitted. Either the
NUMBER or the APC may be omitted, but not both.
"Preindex"
`([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
The NUMBER, or the APC, or the REGISTER, or any two of them, may
be omitted. The ONUMBER may be omitted. The REGISTER and the APC
may appear in either order. If both APC and REGISTER are address
registers, and the SIZE and SCALE are omitted, then the first
register is taken as the base register, and the second as the
index register.

File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent
Floating Point
--------------
Packed decimal (P) format floating literals are not supported. Feel
free to add the code!
The floating point formats generated by directives are these.
`.float'
`Single' precision floating point constants.
`.double'
`Double' precision floating point constants.
`.extend'
`.ldouble'
`Extended' precision (`long double') floating point constants.

File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent
680x0 Machine Directives
------------------------
In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.
`.data1'
This directive is identical to a `.data 1' directive.
`.data2'
This directive is identical to a `.data 2' directive.
`.even'
This directive is a special case of the `.align' directive; it
aligns the output to an even byte boundary.
`.skip'
This directive is identical to a `.space' directive.

File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent
Opcodes
-------
* Menu:
* M68K-Branch:: Branch Improvement
* M68K-Chars:: Special Characters

File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes
Branch Improvement
..................
Certain pseudo opcodes are permitted for branch instructions. They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by substituting `j' for `b' at the
start of a Motorola mnemonic.
The following table summarizes the pseudo-operations. A `*' flags
cases that are more fully described after the table:
Displacement
+-------------------------------------------------
| 68020 68000/10
Pseudo-Op |BYTE WORD LONG LONG non-PC relative
+-------------------------------------------------
jbsr |bsrs bsr bsrl jsr jsr
jra |bras bra bral jmp jmp
* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp
* dbXX |dbXX dbXX dbXX; bra; jmpl
* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp
XX: condition
NX: negative of condition XX
`*'--see full description below
`jbsr'
`jra'
These are the simplest jump pseudo-operations; they always map to
one particular machine instruction, depending on the displacement
to the branch target.
`jXX'
Here, `jXX' stands for an entire family of pseudo-operations,
where XX is a conditional branch or condition-code test. The full
list of pseudo-ops in this family is:
jhi jls jcc jcs jne jeq jvc
jvs jpl jmi jge jlt jgt jle
For the cases of non-PC relative displacements and long
displacements on the 68000 or 68010, `as' issues a longer code
fragment in terms of NX, the opposite condition to XX. For
example, for the non-PC relative case:
jXX foo
gives
bNXs oof
jmp foo
oof:
`dbXX'
The full family of pseudo-operations covered here is
dbhi dbls dbcc dbcs dbne dbeq dbvc
dbvs dbpl dbmi dbge dblt dbgt dble
dbf dbra dbt
Other than for word and byte displacements, when the source reads
`dbXX foo', `as' emits
dbXX oo1
bra oo2
oo1:jmpl foo
oo2:
`fjXX'
This family includes
fjne fjeq fjge fjlt fjgt fjle fjf
fjt fjgl fjgle fjnge fjngl fjngle fjngt
fjnle fjnlt fjoge fjogl fjogt fjole fjolt
fjor fjseq fjsf fjsne fjst fjueq fjuge
fjugt fjule fjult fjun
For branch targets that are not PC relative, `as' emits
fbNX oof
jmp foo
oof:
when it encounters `fjXX foo'.

File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes
Special Characters
..................
The immediate character is `#' for Sun compatibility. The
line-comment character is `|' (unless the `--bitwise-or' option is
used). If a `#' appears at the beginning of a line, it is treated as a
comment unless it looks like `# line file', in which case it is treated
normally.

File: as.info, Node: MIPS-Dependent, Next: SH-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
MIPS Dependent Features
=======================
GNU `as' for MIPS architectures supports several different MIPS
processors, and MIPS ISA levels I through IV. For information about
the MIPS instruction set, see `MIPS RISC Architecture', by Kane and
Heindrich (Prentice-Hall). For an overview of MIPS assembly
conventions, see "Appendix D: Assembly Language Programming" in the
same work.
* Menu:
* MIPS Opts:: Assembler options
* MIPS Object:: ECOFF object code
* MIPS Stabs:: Directives for debugging information
* MIPS ISA:: Directives to override the ISA level
* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
* MIPS insn:: Directive to mark data as an instruction
* MIPS option stack:: Directives to save and restore options

File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent
Assembler options
-----------------
The MIPS configurations of GNU `as' support these special options:
`-G NUM'
This option sets the largest size of an object that can be
referenced implicitly with the `gp' register. It is only accepted
for targets that use ECOFF format. The default value is 8.
`-EB'
`-EL'
Any MIPS configuration of `as' can select big-endian or
little-endian output at run time (unlike the other GNU development
tools, which must be configured for one or the other). Use `-EB'
to select big-endian output, and `-EL' for little-endian.
`-mips1'
`-mips2'
`-mips3'
`-mips4'
Generate code for a particular MIPS Instruction Set Architecture
level. `-mips1' corresponds to the R2000 and R3000 processors,
`-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
and `-mips4' to the R8000 and R10000 processors. You can also
switch instruction sets during the assembly; see *Note Directives
to override the ISA level: MIPS ISA.
`-mips16'
`-no-mips16'
Generate code for the MIPS 16 processor. This is equivalent to
putting `.set mips16' at the start of the assembly file.
`-no-mips16' turns off this option.
`-m4650'
`-no-m4650'
Generate code for the MIPS R4650 chip. This tells the assembler
to accept the `mad' and `madu' instruction, and to not schedule
`nop' instructions around accesses to the `HI' and `LO' registers.
`-no-m4650' turns off this option.
`-m4010'
`-no-m4010'
Generate code for the LSI R4010 chip. This tells the assembler to
accept the R4010 specific instructions (`addciu', `ffc', etc.),
and to not schedule `nop' instructions around accesses to the `HI'
and `LO' registers. `-no-m4010' turns off this option.
`-mcpu=CPU'
Generate code for a particular MIPS cpu. This has little effect
on the assembler, but it is passed by `gcc'.
`-nocpp'
This option is ignored. It is accepted for command-line
compatibility with other assemblers, which use it to turn off C
style preprocessing. With GNU `as', there is no need for
`-nocpp', because the GNU assembler itself never runs the C
preprocessor.
`--trap'
`--no-break'
`as' automatically macro expands certain division and
multiplication instructions to check for overflow and division by
zero. This option causes `as' to generate code to take a trap
exception rather than a break exception when an error is detected.
The trap instructions are only supported at Instruction Set
Architecture level 2 and higher.
`--break'
`--no-trap'
Generate code to take a break exception rather than a trap
exception when an error is detected. This is the default.

File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent
MIPS ECOFF object code
----------------------
Assembling for a MIPS ECOFF target supports some additional sections
besides the usual `.text', `.data' and `.bss'. The additional sections
are `.rdata', used for read-only data, `.sdata', used for small data,
and `.sbss', used for small common objects.
When assembling for ECOFF, the assembler uses the `$gp' (`$28')
register to form the address of a "small object". Any object in the
`.sdata' or `.sbss' sections is considered "small" in this sense. For
external objects, or for objects in the `.bss' section, you can use the
`gcc' `-G' option to control the size of objects addressed via `$gp';
the default value is 8, meaning that a reference to any object eight
bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from
using the `$gp' register on the basis of object size (but the assembler
uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of
an object in the `.bss' section is set by the `.comm' or `.lcomm'
directive that defines it. The size of an external object may be set
with the `.extern' directive. For example, `.extern sym,4' declares
that the object at `sym' is 4 bytes in length, whie leaving `sym'
otherwise undefined.
Using small ECOFF objects requires linker support, and assumes that
the `$gp' register is correctly initialized (normally done
automatically by the startup code). MIPS ECOFF assembly code must not
modify the `$gp' register.

File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent
Directives for debugging information
------------------------------------
MIPS ECOFF `as' supports several directives used for generating
debugging information which are not support by traditional MIPS
assemblers. These are `.def', `.endef', `.dim', `.file', `.scl',
`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'.
The debugging information generated by the three `.stab' directives can
only be read by GDB, not by traditional MIPS debuggers (this
enhancement is required to fully support C++ debugging). These
directives are primarily used by compilers, not assembly language
programmers!

File: as.info, Node: MIPS ISA, Next: MIPS autoextend, Prev: MIPS Stabs, Up: MIPS-Dependent
Directives to override the ISA level
------------------------------------
GNU `as' supports an additional directive to change the MIPS
Instruction Set Architecture level on the fly: `.set mipsN'. N should
be a number from 0 to 4. A value from 1 to 4 makes the assembler
accept instructions for the corresponding ISA level, from that point on
in the assembly. `.set mipsN' affects not only which instructions are
permitted, but also how certain macros are expanded. `.set mips0'
restores the ISA level to its original level: either the level you
selected with command line options, or the default for your
configuration. You can use this feature to permit specific R4000
instructions while assembling in 32 bit mode. Use this directive with
care!
The directive `.set mips16' puts the assembler into MIPS 16 mode, in
which it will assemble instructions for the MIPS 16 processor. Use
`.set nomips16' to return to normal 32 bit mode.
Traditional MIPS assemblers do not support this directive.

File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS ISA, Up: MIPS-Dependent
Directives for extending MIPS 16 bit instructions
-------------------------------------------------
By default, MIPS 16 instructions are automatically extended to 32
bits when necessary. The directive `.set noautoextend' will turn this
off. When `.set noautoextend' is in effect, any 32 bit instruction
must be explicitly extended with the `.e' modifier (e.g., `li.e
$4,1000'). The directive `.set autoextend' may be used to once again
automatically extend instructions when necessary.
This directive is only meaningful when in MIPS 16 mode. Traditional
MIPS assemblers do not support this directive.

File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent
Directive to mark data as an instruction
----------------------------------------
The `.insn' directive tells `as' that the following data is actually
instructions. This makes a difference in MIPS 16 mode: when loading
the address of a label which precedes instructions, `as' automatically
adds 1 to the value, so that jumping to the loaded address will do the
right thing.

File: as.info, Node: MIPS option stack, Prev: MIPS insn, Up: MIPS-Dependent
Directives to save and restore options
--------------------------------------
The directives `.set push' and `.set pop' may be used to save and
restore the current settings for all the options which are controlled
by `.set'. The `.set push' directive saves the current settings on a
stack. The `.set pop' directive pops the stack and restores the
settings.
These directives can be useful inside an macro which must change an
option such as the ISA level or instruction reordering but does not want
to change the state of the code which invoked the macro.
Traditional MIPS assemblers do not support these directives.

File: as.info, Node: SH-Dependent, Next: Sparc-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
Hitachi SH Dependent Features
=============================
* Menu:
* SH Options:: Options
* SH Syntax:: Syntax
* SH Floating Point:: Floating Point
* SH Directives:: SH Machine Directives
* SH Opcodes:: Opcodes

File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent
Options
-------
`as' has no additional command-line options for the Hitachi SH
family.

File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent
Syntax
------
* Menu:
* SH-Chars:: Special Characters
* SH-Regs:: Register Names
* SH-Addressing:: Addressing Modes

File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax
Special Characters
..................
`!' is the line comment character.
You can use `;' instead of a newline to separate statements.
Since `$' has no special meaning, you may use it in symbol names.

File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax
Register Names
..............
You can use the predefined symbols `r0', `r1', `r2', `r3', `r4',
`r5', `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and
`r15' to refer to the SH registers.
The SH also has these control registers:
`pr'
procedure register (holds return address)
`pc'
program counter
`mach'
`macl'
high and low multiply accumulator registers
`sr'
status register
`gbr'
global base register
`vbr'
vector base register (for interrupt vectors)

File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax
Addressing Modes
................
`as' understands the following addressing modes for the SH. `RN' in
the following refers to any of the numbered registers, but *not* the
control registers.
`RN'
Register direct
`@RN'
Register indirect
`@-RN'
Register indirect with pre-decrement
`@RN+'
Register indirect with post-increment
`@(DISP, RN)'
Register indirect with displacement
`@(R0, RN)'
Register indexed
`@(DISP, GBR)'
`GBR' offset
`@(R0, GBR)'
GBR indexed
`ADDR'
`@(DISP, PC)'
PC relative address (for branch or for addressing memory). The
`as' implementation allows you to use the simpler form ADDR
anywhere a PC relative address is called for; the alternate form
is supported for compatibility with other assemblers.
`#IMM'
Immediate data

File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent
Floating Point
--------------
The SH family has no hardware floating point, but the `.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.

File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent
SH Machine Directives
---------------------
`uaword'
`ualong'
`as' will issue a warning when a misaligned `.word' or `.long'
directive is used. You may use `.uaword' or `.ualong' to indicate
that the value is intentionally misaligned.

File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
Opcodes
-------
For detailed information on the SH machine instruction set, see
`SH-Microcomputer User's Manual' (Hitachi Micro Systems, Inc.).
`as' implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because `as' supports a simpler form of PC-relative addressing, you may
simply write (for example)
mov.l bar,r0
where other assemblers might require an explicit displacement to `bar'
from the program counter:
mov.l @(DISP, PC)
Here is a summary of SH opcodes:
Legend:
Rn a numbered register
Rm another numbered register
#imm immediate data
disp displacement
disp8 8-bit displacement
disp12 12-bit displacement
add #imm,Rn lds.l @Rn+,PR
add Rm,Rn mac.w @Rm+,@Rn+
addc Rm,Rn mov #imm,Rn
addv Rm,Rn mov Rm,Rn
and #imm,R0 mov.b Rm,@(R0,Rn)
and Rm,Rn mov.b Rm,@-Rn
and.b #imm,@(R0,GBR) mov.b Rm,@Rn
bf disp8 mov.b @(disp,Rm),R0
bra disp12 mov.b @(disp,GBR),R0
bsr disp12 mov.b @(R0,Rm),Rn
bt disp8 mov.b @Rm+,Rn
clrmac mov.b @Rm,Rn
clrt mov.b R0,@(disp,Rm)
cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
cmp/gt Rm,Rn mov.l Rm,@-Rn
cmp/hi Rm,Rn mov.l Rm,@Rn
cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
cmp/pl Rn mov.l @(disp,GBR),R0
cmp/pz Rn mov.l @(disp,PC),Rn
cmp/str Rm,Rn mov.l @(R0,Rm),Rn
div0s Rm,Rn mov.l @Rm+,Rn
div0u mov.l @Rm,Rn
div1 Rm,Rn mov.l R0,@(disp,GBR)
exts.b Rm,Rn mov.w Rm,@(R0,Rn)
exts.w Rm,Rn mov.w Rm,@-Rn
extu.b Rm,Rn mov.w Rm,@Rn
extu.w Rm,Rn mov.w @(disp,Rm),R0
jmp @Rn mov.w @(disp,GBR),R0
jsr @Rn mov.w @(disp,PC),Rn
ldc Rn,GBR mov.w @(R0,Rm),Rn
ldc Rn,SR mov.w @Rm+,Rn
ldc Rn,VBR mov.w @Rm,Rn
ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
ldc.l @Rn+,VBR mova @(disp,PC),R0
lds Rn,MACH movt Rn
lds Rn,MACL muls Rm,Rn
lds Rn,PR mulu Rm,Rn
lds.l @Rn+,MACH neg Rm,Rn
lds.l @Rn+,MACL negc Rm,Rn
nop stc VBR,Rn
not Rm,Rn stc.l GBR,@-Rn
or #imm,R0 stc.l SR,@-Rn
or Rm,Rn stc.l VBR,@-Rn
or.b #imm,@(R0,GBR) sts MACH,Rn
rotcl Rn sts MACL,Rn
rotcr Rn sts PR,Rn
rotl Rn sts.l MACH,@-Rn
rotr Rn sts.l MACL,@-Rn
rte sts.l PR,@-Rn
rts sub Rm,Rn
sett subc Rm,Rn
shal Rn subv Rm,Rn
shar Rn swap.b Rm,Rn
shll Rn swap.w Rm,Rn
shll16 Rn tas.b @Rn
shll2 Rn trapa #imm
shll8 Rn tst #imm,R0
shlr Rn tst Rm,Rn
shlr16 Rn tst.b #imm,@(R0,GBR)
shlr2 Rn xor #imm,R0
shlr8 Rn xor Rm,Rn
sleep xor.b #imm,@(R0,GBR)
stc GBR,Rn xtrct Rm,Rn
stc SR,Rn

File: as.info, Node: Sparc-Dependent, Next: V850-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
SPARC Dependent Features
========================
* Menu:
* Sparc-Opts:: Options
* Sparc-Aligned-Data:: Option to enforce aligned data
* Sparc-Float:: Floating Point
* Sparc-Directives:: Sparc Machine Directives

File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
Options
-------
The SPARC chip family includes several successive levels, using the
same core instruction set, but including a few additional instructions
at each level. There are exceptions to this however. For details on
what instructions each variant supports, please see the chip's
architecture reference manual.
By default, `as' assumes the core instruction set (SPARC v6), but
"bumps" the architecture level as needed: it switches to successively
higher architectures as it encounters instructions that only exist in
the higher levels.
If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
passed sparclite by default, an option must be passed to enable the v9
instructions.
GAS treats sparclite as being compatible with v8, unless an
architecture is explicitly requested. SPARC v9 is always incompatible
with sparclite.
`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
`-Av8plus | -Av8plusa | -Av9 | -Av9a'
Use one of the `-A' options to select one of the SPARC
architectures explicitly. If you select an architecture
explicitly, `as' reports a fatal error if it encounters an
instruction or feature requiring an incompatible or higher level.
`-Av8plus' and `-Av8plusa' select a 32 bit environment.
`-Av9' and `-Av9a' select a 64 bit environment and are not
available unless GAS is explicitly configured with 64 bit
environment support.
`-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
UltraSPARC extensions.
`-xarch=v8plus | -xarch=v8plusa'
For compatibility with the Solaris v9 assembler. These options are
equivalent to -Av8plus and -Av8plusa, respectively.
`-bump'
Warn whenever it is necessary to switch to another level. If an
architecture level is explicitly requested, GAS will not issue
warnings until that level is reached, and will then bump the level
as required (except between incompatible levels).
`-32 | -64'
Select the word size, either 32 bits or 64 bits. These options
are only available with the ELF object file format, and require
that the necessary BFD support has been included.

File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Float, Prev: Sparc-Opts, Up: Sparc-Dependent
Enforcing aligned data
----------------------
SPARC GAS normally permits data to be misaligned. For example, it
permits the `.long' pseudo-op to be used on a byte boundary. However,
the native SunOS and Solaris assemblers issue an error when they see
misaligned data.
You can use the `--enforce-aligned-data' option to make SPARC GAS
also issue an error about misaligned data, just as the SunOS and Solaris
assemblers do.
The `--enforce-aligned-data' option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
data structures (structures defined using the `packed' attribute). You
may have to assemble with GAS in order to initialize packed data
structures in your own code.

File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
Floating Point
--------------
The Sparc uses IEEE floating-point numbers.

File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
Sparc Machine Directives
------------------------
The Sparc version of `as' supports the following additional machine
directives:
`.align'
This must be followed by the desired alignment in bytes.
`.common'
This must be followed by a symbol name, a positive number, and
`"bss"'. This behaves somewhat like `.comm', but the syntax is
different.
`.half'
This is functionally identical to `.short'.
`.proc'
This directive is ignored. Any text following it on the same line
is also ignored.
`.reserve'
This must be followed by a symbol name, a positive number, and
`"bss"'. This behaves somewhat like `.lcomm', but the syntax is
different.
`.seg'
This must be followed by `"text"', `"data"', or `"data1"'. It
behaves like `.text', `.data', or `.data 1'.
`.skip'
This is functionally identical to the `.space' directive.
`.word'
On the Sparc, the `.word' directive produces 32 bit values,
instead of the 16 bit values it produces on many other machines.
`.xword'
On the Sparc V9 processor, the `.xword' directive produces 64 bit
values.

File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
Z8000 Dependent Features
========================
The Z8000 as supports both members of the Z8000 family: the
unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
24 bit addresses.
When the assembler is in unsegmented mode (specified with the
`unsegm' directive), an address takes up one word (16 bit) sized
register. When the assembler is in segmented mode (specified with the
`segm' directive), a 24-bit address takes up a long (32 bit) register.
*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
of other Z8000 specific assembler directives.
* Menu:
* Z8000 Options:: No special command-line options for Z8000
* Z8000 Syntax:: Assembler syntax for the Z8000
* Z8000 Directives:: Special directives for the Z8000
* Z8000 Opcodes:: Opcodes

File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
Options
-------
`as' has no additional command-line options for the Zilog Z8000
family.

File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
Syntax
------
* Menu:
* Z8000-Chars:: Special Characters
* Z8000-Regs:: Register Names
* Z8000-Addressing:: Addressing Modes

File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
Special Characters
..................
`!' is the line comment character.
You can use `;' instead of a newline to separate statements.

File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
Register Names
..............
The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can
refer to different sized groups of registers by register number, with
the prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq'
for 64 bit registers. You can also refer to the contents of the first
eight (of the sixteen 16 bit registers) by bytes. They are named `rNh'
and `rNl'.
*byte registers*
r0l r0h r1h r1l r2h r2l r3h r3l
r4h r4l r5h r5l r6h r6l r7h r7l
*word registers*
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
*long word registers*
rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
*quad word registers*
rq0 rq4 rq8 rq12

File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
Addressing Modes
................
as understands the following addressing modes for the Z8000:
`rN'
Register direct
`@rN'
Indirect register
`ADDR'
Direct: the 16 bit or 24 bit address (depending on whether the
assembler is in segmented or unsegmented mode) of the operand is
in the instruction.
`address(rN)'
Indexed: the 16 or 24 bit address is added to the 16 bit register
to produce the final address in memory of the operand.
`rN(#IMM)'
Base Address: the 16 or 24 bit register is added to the 16 bit sign
extended immediate displacement to produce the final address in
memory of the operand.
`rN(rM)'
Base Index: the 16 or 24 bit register rN is added to the sign
extended 16 bit index register rM to produce the final address in
memory of the operand.
`#XX'
Immediate data XX.

File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
Assembler Directives for the Z8000
----------------------------------
The Z8000 port of as includes these additional assembler directives,
for compatibility with other Z8000 assemblers. As shown, these do not
begin with `.' (unlike the ordinary as directives).
`segm'
Generates code for the segmented Z8001.
`unsegm'
Generates code for the unsegmented Z8002.
`name'
Synonym for `.file'
`global'
Synonym for `.global'
`wval'
Synonym for `.word'
`lval'
Synonym for `.long'
`bval'
Synonym for `.byte'
`sval'
Assemble a string. `sval' expects one string literal, delimited by
single quotes. It assembles each byte of the string into
consecutive addresses. You can use the escape sequence `%XX'
(where XX represents a two-digit hexadecimal number) to represent
the character whose ASCII value is XX. Use this feature to
describe single quote and other characters that may not appear in
string literals as themselves. For example, the C statement
`char *a = "he said \"it's 50% off\"";' is represented in Z8000
assembly language (shown with the assembler output in hex at the
left) as
68652073 sval 'he said %22it%27s 50%25 off%22%00'
61696420
22697427
73203530
25206F66
662200
`rsect'
synonym for `.section'
`block'
synonym for `.space'
`even'
special case of `.align'; aligns output to even byte boundary.
Reference in New Issue View Git Blame Copy Permalink