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.include "macro.inc"
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/* assembler directives */
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.set noat /* allow manual use of $at */
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.set noreorder /* don't insert nops after branches */
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.set gp=64 /* allow use of 64-bit general purpose registers */
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.section .text, "ax"
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/* Generated by spimdisasm 1.11.1 */
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# Handwritten function
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glabel osWritebackDCache
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/* 3CC20 80061820 18A00011 */ blez $a1, .LJP_80061868
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/* 3CC24 80061824 00000000 */ nop
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/* 3CC28 80061828 240B2000 */ addiu $t3, $zero, 0x2000
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/* 3CC2C 8006182C 00AB082B */ sltu $at, $a1, $t3
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/* 3CC30 80061830 1020000F */ beqz $at, .LJP_80061870
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/* 3CC34 80061834 00000000 */ nop
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/* 3CC38 80061838 00804021 */ addu $t0, $a0, $zero
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/* 3CC3C 8006183C 00854821 */ addu $t1, $a0, $a1
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/* 3CC40 80061840 0109082B */ sltu $at, $t0, $t1
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/* 3CC44 80061844 10200008 */ beqz $at, .LJP_80061868
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/* 3CC48 80061848 00000000 */ nop
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/* 3CC4C 8006184C 2529FFF0 */ addiu $t1, $t1, -0x10
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/* 3CC50 80061850 310A000F */ andi $t2, $t0, 0xF
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/* 3CC54 80061854 010A4023 */ subu $t0, $t0, $t2
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.LJP_80061858:
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/* 3CC58 80061858 BD190000 */ cache 0x19, 0x0($t0) # handwritten instruction
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/* 3CC5C 8006185C 0109082B */ sltu $at, $t0, $t1
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/* 3CC60 80061860 1420FFFD */ bnez $at, .LJP_80061858
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/* 3CC64 80061864 25080010 */ addiu $t0, $t0, 0x10
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.LJP_80061868:
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/* 3CC68 80061868 03E00008 */ jr $ra
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/* 3CC6C 8006186C 00000000 */ nop
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.LJP_80061870:
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/* 3CC70 80061870 3C088000 */ lui $t0, 0x8000
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/* 3CC74 80061874 010B4821 */ addu $t1, $t0, $t3
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/* 3CC78 80061878 2529FFF0 */ addiu $t1, $t1, -0x10
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.LJP_8006187C:
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/* 3CC7C 8006187C BD010000 */ cache 0x01, 0x0($t0) # handwritten instruction
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/* 3CC80 80061880 0109082B */ sltu $at, $t0, $t1
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/* 3CC84 80061884 1420FFFD */ bnez $at, .LJP_8006187C
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/* 3CC88 80061888 25080010 */ addiu $t0, $t0, (0x80000010 & 0xFFFF)
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/* 3CC8C 8006188C 03E00008 */ jr $ra
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/* 3CC90 80061890 00000000 */ nop
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/* 3CC94 80061894 00000000 */ nop
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/* 3CC98 80061898 00000000 */ nop
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/* 3CC9C 8006189C 00000000 */ nop
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