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.include "macro.inc"
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/* assembler directives */
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.set noat /* allow manual use of $at */
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.set noreorder /* don't insert nops after branches */
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.set gp=64 /* allow use of 64-bit general purpose registers */
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.section .text, "ax"
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/* Generated by spimdisasm 1.11.1 */
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# Handwritten function
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glabel osInvalICache
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/* 3CBA0 800617A0 18A00011 */ blez $a1, .LJP_800617E8
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/* 3CBA4 800617A4 00000000 */ nop
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/* 3CBA8 800617A8 240B4000 */ addiu $t3, $zero, 0x4000
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/* 3CBAC 800617AC 00AB082B */ sltu $at, $a1, $t3
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/* 3CBB0 800617B0 1020000F */ beqz $at, .LJP_800617F0
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/* 3CBB4 800617B4 00000000 */ nop
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/* 3CBB8 800617B8 00804021 */ addu $t0, $a0, $zero
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/* 3CBBC 800617BC 00854821 */ addu $t1, $a0, $a1
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/* 3CBC0 800617C0 0109082B */ sltu $at, $t0, $t1
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/* 3CBC4 800617C4 10200008 */ beqz $at, .LJP_800617E8
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/* 3CBC8 800617C8 00000000 */ nop
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/* 3CBCC 800617CC 2529FFE0 */ addiu $t1, $t1, -0x20
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/* 3CBD0 800617D0 310A001F */ andi $t2, $t0, 0x1F
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/* 3CBD4 800617D4 010A4023 */ subu $t0, $t0, $t2
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.LJP_800617D8:
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/* 3CBD8 800617D8 BD100000 */ cache 0x10, 0x0($t0) # handwritten instruction
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/* 3CBDC 800617DC 0109082B */ sltu $at, $t0, $t1
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/* 3CBE0 800617E0 1420FFFD */ bnez $at, .LJP_800617D8
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/* 3CBE4 800617E4 25080020 */ addiu $t0, $t0, 0x20
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.LJP_800617E8:
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/* 3CBE8 800617E8 03E00008 */ jr $ra
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/* 3CBEC 800617EC 00000000 */ nop
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.LJP_800617F0:
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/* 3CBF0 800617F0 3C088000 */ lui $t0, 0x8000
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/* 3CBF4 800617F4 010B4821 */ addu $t1, $t0, $t3
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/* 3CBF8 800617F8 2529FFE0 */ addiu $t1, $t1, -0x20
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.LJP_800617FC:
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/* 3CBFC 800617FC BD000000 */ cache 0x00, 0x0($t0) # handwritten instruction
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/* 3CC00 80061800 0109082B */ sltu $at, $t0, $t1
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/* 3CC04 80061804 1420FFFD */ bnez $at, .LJP_800617FC
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/* 3CC08 80061808 25080020 */ addiu $t0, $t0, (0x80000020 & 0xFFFF)
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/* 3CC0C 8006180C 03E00008 */ jr $ra
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/* 3CC10 80061810 00000000 */ nop
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/* 3CC14 80061814 00000000 */ nop
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/* 3CC18 80061818 00000000 */ nop
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/* 3CC1C 8006181C 00000000 */ nop
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