.include "macro.inc"

# assembler directives
.set noat      # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64     # allow use of 64-bit general purpose registers

.section .text, "ax"

glabel guMtxF2L
/* 42900 80067500 3C014780 */  lui       $at, 0x4780
/* 42904 80067504 44810000 */  mtc1      $at, $f0
/* 42908 80067508 3C19FFFF */  lui       $t9, 0xffff
/* 4290C 8006750C 24B80020 */  addiu     $t8, $a1, 0x20
.L80067510:
/* 42910 80067510 C4840000 */  lwc1      $f4, ($a0)
/* 42914 80067514 46002182 */  mul.s     $f6, $f4, $f0
/* 42918 80067518 4600320D */  trunc.w.s $f8, $f6
/* 4291C 8006751C C48A0004 */  lwc1      $f10, 4($a0)
/* 42920 80067520 46005402 */  mul.s     $f16, $f10, $f0
/* 42924 80067524 4600848D */  trunc.w.s $f18, $f16
/* 42928 80067528 44084000 */  mfc1      $t0, $f8
/* 4292C 8006752C 44099000 */  mfc1      $t1, $f18
/* 42930 80067530 01195024 */  and       $t2, $t0, $t9
/* 42934 80067534 00095C02 */  srl       $t3, $t1, 0x10
/* 42938 80067538 014B6025 */  or        $t4, $t2, $t3
/* 4293C 8006753C ACAC0000 */  sw        $t4, ($a1)
/* 42940 80067540 00086C00 */  sll       $t5, $t0, 0x10
/* 42944 80067544 312EFFFF */  andi      $t6, $t1, 0xffff
/* 42948 80067548 01AE7825 */  or        $t7, $t5, $t6
/* 4294C 8006754C ACAF0020 */  sw        $t7, 0x20($a1)
/* 42950 80067550 24A50004 */  addiu     $a1, $a1, 4
/* 42954 80067554 14B8FFEE */  bne       $a1, $t8, .L80067510
/* 42958 80067558 24840008 */   addiu    $a0, $a0, 8
/* 4295C 8006755C 03E00008 */  jr        $ra
/* 42960 80067560 00000000 */   nop
/* 42964 80067564 00000000 */  nop
/* 42968 80067568 00000000 */  nop
/* 4296C 8006756C 00000000 */  nop
/* 42970 80067570 00000000 */  nop
/* 42974 80067574 00000000 */  nop
/* 42978 80067578 00000000 */  nop
/* 4297C 8006757C 00000000 */  nop