mirror of
https://github.com/pmret/papermario.git
synced 2024-11-18 08:52:40 +01:00
b171712e0e
* match libultra ique pt 1 * add sgidefs.h to include/gcc * recvmesg match + _getcount * add elfpatch.py for those compiled with -mips3 * pt 2 * os/setthreadpri(.data) -> os/thread * os thread matches * os timer matches * pt 4 (erm... 3?) * vitbl * os pi matches * pt. uhmmmm, i've lost track... * os pfs matches * replace elfpatch.py * pt. just forget it... * outsource from ultralib ique branch * . * . 2 * final blow * add egcs compiler to Jenkinsfile * fix errors from CI * minor changes as requested
53 lines
2.4 KiB
ArmAsm
53 lines
2.4 KiB
ArmAsm
.include "macro.inc"
|
|
|
|
/* assembler directives */
|
|
.set noat /* allow manual use of $at */
|
|
.set noreorder /* don't insert nops after branches */
|
|
.set gp=64 /* allow use of 64-bit general purpose registers */
|
|
|
|
.section .text, "ax"
|
|
|
|
/* Generated by spimdisasm 1.11.1 */
|
|
|
|
glabel guScale
|
|
/* 410C0 80065CC0 3C014780 */ lui $at, (0x47800000 >> 16)
|
|
/* 410C4 80065CC4 44812000 */ mtc1 $at, $f4
|
|
/* 410C8 80065CC8 44853000 */ mtc1 $a1, $f6
|
|
/* 410CC 80065CCC 46043202 */ mul.s $f8, $f6, $f4
|
|
/* 410D0 80065CD0 4600428D */ trunc.w.s $f10, $f8
|
|
/* 410D4 80065CD4 44095000 */ mfc1 $t1, $f10
|
|
/* 410D8 80065CD8 00095402 */ srl $t2, $t1, 16
|
|
/* 410DC 80065CDC 000A4400 */ sll $t0, $t2, 16
|
|
/* 410E0 80065CE0 AC880000 */ sw $t0, 0x0($a0)
|
|
/* 410E4 80065CE4 00095400 */ sll $t2, $t1, 16
|
|
/* 410E8 80065CE8 AC8A0020 */ sw $t2, 0x20($a0)
|
|
/* 410EC 80065CEC 44863000 */ mtc1 $a2, $f6
|
|
/* 410F0 80065CF0 46043202 */ mul.s $f8, $f6, $f4
|
|
/* 410F4 80065CF4 4600428D */ trunc.w.s $f10, $f8
|
|
/* 410F8 80065CF8 44095000 */ mfc1 $t1, $f10
|
|
/* 410FC 80065CFC 00094402 */ srl $t0, $t1, 16
|
|
/* 41100 80065D00 AC880008 */ sw $t0, 0x8($a0)
|
|
/* 41104 80065D04 312AFFFF */ andi $t2, $t1, 0xFFFF
|
|
/* 41108 80065D08 AC8A0028 */ sw $t2, 0x28($a0)
|
|
/* 4110C 80065D0C 44873000 */ mtc1 $a3, $f6
|
|
/* 41110 80065D10 46043202 */ mul.s $f8, $f6, $f4
|
|
/* 41114 80065D14 4600428D */ trunc.w.s $f10, $f8
|
|
/* 41118 80065D18 44095000 */ mfc1 $t1, $f10
|
|
/* 4111C 80065D1C 00095402 */ srl $t2, $t1, 16
|
|
/* 41120 80065D20 000A4400 */ sll $t0, $t2, 16
|
|
/* 41124 80065D24 AC880014 */ sw $t0, 0x14($a0)
|
|
/* 41128 80065D28 00095400 */ sll $t2, $t1, 16
|
|
/* 4112C 80065D2C AC8A0034 */ sw $t2, 0x34($a0)
|
|
/* 41130 80065D30 24080001 */ addiu $t0, $zero, 0x1
|
|
/* 41134 80065D34 AC88001C */ sw $t0, 0x1C($a0)
|
|
/* 41138 80065D38 AC800004 */ sw $zero, 0x4($a0)
|
|
/* 4113C 80065D3C AC80000C */ sw $zero, 0xC($a0)
|
|
/* 41140 80065D40 AC800010 */ sw $zero, 0x10($a0)
|
|
/* 41144 80065D44 AC800018 */ sw $zero, 0x18($a0)
|
|
/* 41148 80065D48 AC800024 */ sw $zero, 0x24($a0)
|
|
/* 4114C 80065D4C AC80002C */ sw $zero, 0x2C($a0)
|
|
/* 41150 80065D50 AC800030 */ sw $zero, 0x30($a0)
|
|
/* 41154 80065D54 AC800038 */ sw $zero, 0x38($a0)
|
|
/* 41158 80065D58 03E00008 */ jr $ra
|
|
/* 4115C 80065D5C AC80003C */ sw $zero, 0x3C($a0)
|