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47 lines
1.8 KiB
ArmAsm
47 lines
1.8 KiB
ArmAsm
.include "macro.inc"
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# assembler directives
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.set noat # allow manual use of $at
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.set noreorder # don't insert nops after branches
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.set gp=64 # allow use of 64-bit general purpose registers
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.section .text, "ax"
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glabel osWritebackDCache
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/* 3CC50 80061850 18A00011 */ blez $a1, .L80061898
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/* 3CC54 80061854 00000000 */ nop
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/* 3CC58 80061858 240B2000 */ addiu $t3, $zero, 0x2000
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/* 3CC5C 8006185C 00AB082B */ sltu $at, $a1, $t3
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/* 3CC60 80061860 1020000F */ beqz $at, .L800618A0
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/* 3CC64 80061864 00000000 */ nop
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/* 3CC68 80061868 00804021 */ addu $t0, $a0, $zero
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/* 3CC6C 8006186C 00854821 */ addu $t1, $a0, $a1
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/* 3CC70 80061870 0109082B */ sltu $at, $t0, $t1
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/* 3CC74 80061874 10200008 */ beqz $at, .L80061898
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/* 3CC78 80061878 00000000 */ nop
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/* 3CC7C 8006187C 2529FFF0 */ addiu $t1, $t1, -0x10
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/* 3CC80 80061880 310A000F */ andi $t2, $t0, 0xf
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/* 3CC84 80061884 010A4023 */ subu $t0, $t0, $t2
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.L80061888:
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/* 3CC88 80061888 BD190000 */ cache 0x19, ($t0)
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/* 3CC8C 8006188C 0109082B */ sltu $at, $t0, $t1
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/* 3CC90 80061890 1420FFFD */ bnez $at, .L80061888
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/* 3CC94 80061894 25080010 */ addiu $t0, $t0, 0x10
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.L80061898:
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/* 3CC98 80061898 03E00008 */ jr $ra
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/* 3CC9C 8006189C 00000000 */ nop
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.L800618A0:
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/* 3CCA0 800618A0 3C088000 */ lui $t0, 0x8000
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/* 3CCA4 800618A4 010B4821 */ addu $t1, $t0, $t3
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/* 3CCA8 800618A8 2529FFF0 */ addiu $t1, $t1, -0x10
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.L800618AC:
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/* 3CCAC 800618AC BD010000 */ cache 1, ($t0)
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/* 3CCB0 800618B0 0109082B */ sltu $at, $t0, $t1
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/* 3CCB4 800618B4 1420FFFD */ bnez $at, .L800618AC
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/* 3CCB8 800618B8 25080010 */ addiu $t0, $t0, 0x10
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/* 3CCBC 800618BC 03E00008 */ jr $ra
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/* 3CCC0 800618C0 00000000 */ nop
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/* 3CCC4 800618C4 00000000 */ nop
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/* 3CCC8 800618C8 00000000 */ nop
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/* 3CCCC 800618CC 00000000 */ nop
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