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47 lines
1.8 KiB
ArmAsm
47 lines
1.8 KiB
ArmAsm
.include "macro.inc"
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# assembler directives
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.set noat # allow manual use of $at
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.set noreorder # don't insert nops after branches
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.set gp=64 # allow use of 64-bit general purpose registers
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.section .text, "ax"
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glabel osInvalICache
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/* 3CBD0 800617D0 18A00011 */ blez $a1, .L80061818
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/* 3CBD4 800617D4 00000000 */ nop
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/* 3CBD8 800617D8 240B4000 */ addiu $t3, $zero, 0x4000
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/* 3CBDC 800617DC 00AB082B */ sltu $at, $a1, $t3
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/* 3CBE0 800617E0 1020000F */ beqz $at, .L80061820
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/* 3CBE4 800617E4 00000000 */ nop
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/* 3CBE8 800617E8 00804021 */ addu $t0, $a0, $zero
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/* 3CBEC 800617EC 00854821 */ addu $t1, $a0, $a1
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/* 3CBF0 800617F0 0109082B */ sltu $at, $t0, $t1
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/* 3CBF4 800617F4 10200008 */ beqz $at, .L80061818
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/* 3CBF8 800617F8 00000000 */ nop
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/* 3CBFC 800617FC 2529FFE0 */ addiu $t1, $t1, -0x20
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/* 3CC00 80061800 310A001F */ andi $t2, $t0, 0x1f
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/* 3CC04 80061804 010A4023 */ subu $t0, $t0, $t2
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.L80061808:
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/* 3CC08 80061808 BD100000 */ cache 0x10, ($t0)
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/* 3CC0C 8006180C 0109082B */ sltu $at, $t0, $t1
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/* 3CC10 80061810 1420FFFD */ bnez $at, .L80061808
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/* 3CC14 80061814 25080020 */ addiu $t0, $t0, 0x20
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.L80061818:
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/* 3CC18 80061818 03E00008 */ jr $ra
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/* 3CC1C 8006181C 00000000 */ nop
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.L80061820:
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/* 3CC20 80061820 3C088000 */ lui $t0, 0x8000
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/* 3CC24 80061824 010B4821 */ addu $t1, $t0, $t3
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/* 3CC28 80061828 2529FFE0 */ addiu $t1, $t1, -0x20
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.L8006182C:
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/* 3CC2C 8006182C BD000000 */ cache 0, ($t0)
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/* 3CC30 80061830 0109082B */ sltu $at, $t0, $t1
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/* 3CC34 80061834 1420FFFD */ bnez $at, .L8006182C
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/* 3CC38 80061838 25080020 */ addiu $t0, $t0, 0x20
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/* 3CC3C 8006183C 03E00008 */ jr $ra
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/* 3CC40 80061840 00000000 */ nop
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/* 3CC44 80061844 00000000 */ nop
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/* 3CC48 80061848 00000000 */ nop
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/* 3CC4C 8006184C 00000000 */ nop
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