mirror of
https://github.com/pmret/papermario.git
synced 2024-11-08 20:12:30 +01:00
ecb65c720a
* Change splat subrepo to use main branch * git subrepo pull --force tools/splat subrepo: subdir: "tools/splat" merged: "fbf3fa68a7" upstream: origin: "https://github.com/ethteck/splat.git" branch: "main" commit: "fbf3fa68a7" git-subrepo: version: "0.4.5" origin: "https://github.com/ingydotnet/git-subrepo" commit: "aa416e4" * building now * vram classes in the us yaml * more progrezz * more * prepare to deal with the shiftable build * revert a couple things * bring the yaml more in line with the old one while debugging * got statis * vacuum * git subrepo pull --force tools/splat subrepo: subdir: "tools/splat" merged: "d6490bb877" upstream: origin: "https://github.com/ethteck/splat.git" branch: "main" commit: "d6490bb877" git-subrepo: version: "0.4.5" origin: "https://github.com/ingydotnet/git-subrepo" commit: "aa416e4" * clean
75 lines
2.2 KiB
Plaintext
75 lines
2.2 KiB
Plaintext
SECTIONS
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{
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__romPos = 0;
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_gp = 0x0;
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header_ROM_START = __romPos;
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header_VRAM = ADDR(.header);
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.header : AT(header_ROM_START) SUBALIGN(16)
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{
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FILL(0x00000000);
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header_DATA_START = .;
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header_s = .;
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build/split/asm/header.s.o(.data);
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header_DATA_END = .;
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header_DATA_SIZE = ABSOLUTE(header_DATA_END - header_DATA_START);
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}
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__romPos += SIZEOF(.header);
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header_ROM_END = __romPos;
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header_VRAM_END = .;
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dummy_ipl3_ROM_START = __romPos;
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dummy_ipl3_VRAM = ADDR(.dummy_ipl3);
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.dummy_ipl3 0xA4000040 : AT(dummy_ipl3_ROM_START) SUBALIGN(16)
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{
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FILL(0x00000000);
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dummy_ipl3_DATA_START = .;
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dummy_ipl3_bin = .;
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build/split/assets/dummy_ipl3.bin.o(.data);
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dummy_ipl3_DATA_END = .;
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dummy_ipl3_DATA_SIZE = ABSOLUTE(dummy_ipl3_DATA_END - dummy_ipl3_DATA_START);
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}
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__romPos += SIZEOF(.dummy_ipl3);
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__romPos = ALIGN(__romPos, 16);
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dummy_ipl3_ROM_END = __romPos;
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dummy_ipl3_VRAM_END = .;
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boot_ROM_START = __romPos;
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boot_VRAM = ADDR(.boot);
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.boot 0x80000400 : AT(boot_ROM_START) SUBALIGN(16)
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{
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FILL(0x00000000);
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boot_TEXT_START = .;
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build/split/src/main.c.o(.text);
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build/split/asm/handwritten.s.o(.text);
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boot_TEXT_END = .;
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boot_TEXT_SIZE = ABSOLUTE(boot_TEXT_END - boot_TEXT_START);
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boot_DATA_START = .;
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main_data__s = .;
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build/split/asm/data/main.data.s.o(.data);
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boot_DATA_END = .;
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boot_DATA_SIZE = ABSOLUTE(boot_DATA_END - boot_DATA_START);
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boot_RODATA_START = .;
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build/split/asm/data/main.rodata.s.o(.rodata);
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boot_RODATA_END = .;
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boot_RODATA_SIZE = ABSOLUTE(boot_RODATA_END - boot_RODATA_START);
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}
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boot_bss_VRAM = ADDR(.boot_bss);
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.boot_bss (NOLOAD) : SUBALIGN(16)
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{
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FILL(0x00000000);
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boot_BSS_START = .;
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build/split/asm/data/main.bss.s.o(.bss);
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boot_BSS_END = .;
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boot_BSS_SIZE = ABSOLUTE(boot_BSS_END - boot_BSS_START);
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}
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__romPos += SIZEOF(.boot);
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__romPos = ALIGN(__romPos, 16);
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boot_ROM_END = __romPos;
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boot_VRAM_END = .;
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/DISCARD/ :
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{
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*(*);
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}
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}
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