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b171712e0e
* match libultra ique pt 1 * add sgidefs.h to include/gcc * recvmesg match + _getcount * add elfpatch.py for those compiled with -mips3 * pt 2 * os/setthreadpri(.data) -> os/thread * os thread matches * os timer matches * pt 4 (erm... 3?) * vitbl * os pi matches * pt. uhmmmm, i've lost track... * os pfs matches * replace elfpatch.py * pt. just forget it... * outsource from ultralib ique branch * . * . 2 * final blow * add egcs compiler to Jenkinsfile * fix errors from CI * minor changes as requested
37 lines
1.5 KiB
ArmAsm
37 lines
1.5 KiB
ArmAsm
.include "macro.inc"
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/* assembler directives */
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.set noat /* allow manual use of $at */
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.set noreorder /* don't insert nops after branches */
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.set gp=64 /* allow use of 64-bit general purpose registers */
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.section .text, "ax"
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/* Generated by spimdisasm 1.11.1 */
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glabel guNormalize
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/* 47040 8006BC40 C4840000 */ lwc1 $f4, 0x0($a0)
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/* 47044 8006BC44 C4A60000 */ lwc1 $f6, 0x0($a1)
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/* 47048 8006BC48 C4C80000 */ lwc1 $f8, 0x0($a2)
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/* 4704C 8006BC4C 46042282 */ mul.s $f10, $f4, $f4
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/* 47050 8006BC50 3C083F80 */ lui $t0, (0x3F800000 >> 16)
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/* 47054 8006BC54 46063402 */ mul.s $f16, $f6, $f6
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/* 47058 8006BC58 46105480 */ add.s $f18, $f10, $f16
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/* 4705C 8006BC5C 46084402 */ mul.s $f16, $f8, $f8
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/* 47060 8006BC60 46128280 */ add.s $f10, $f16, $f18
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/* 47064 8006BC64 44889000 */ mtc1 $t0, $f18
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/* 47068 8006BC68 46005404 */ sqrt.s $f16, $f10
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/* 4706C 8006BC6C 46109283 */ div.s $f10, $f18, $f16
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/* 47070 8006BC70 460A2402 */ mul.s $f16, $f4, $f10
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/* 47074 8006BC74 00000000 */ nop
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/* 47078 8006BC78 460A3482 */ mul.s $f18, $f6, $f10
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/* 4707C 8006BC7C 00000000 */ nop
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/* 47080 8006BC80 460A4102 */ mul.s $f4, $f8, $f10
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/* 47084 8006BC84 E4900000 */ swc1 $f16, 0x0($a0)
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/* 47088 8006BC88 E4B20000 */ swc1 $f18, 0x0($a1)
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/* 4708C 8006BC8C 03E00008 */ jr $ra
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/* 47090 8006BC90 E4C40000 */ swc1 $f4, 0x0($a2)
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/* 47094 8006BC94 00000000 */ nop
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/* 47098 8006BC98 00000000 */ nop
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/* 4709C 8006BC9C 00000000 */ nop
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