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llvm-mirror/test/MC/RISCV/fde-reloc.s

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[RISCV][NFC] Add tests that capture current encodings for DWARF EH Items which are known to be wrong/different vs GCC are marked as TODO and will be address in follow-up patches. llvm-svn: 366326
2019-07-17 13:48:49 +00:00
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=NORELAX-RELOC %s
func:
.cfi_startproc
ret
.cfi_endproc
# RELAX-RELOC: Section (4) .rela.eh_frame {
[RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit <https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>, the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375
2019-08-20 12:32:31 +00:00
# RELAX-RELOC-NEXT: 0x1C R_RISCV_32_PCREL - 0x0
[RISCV][NFC] Add tests that capture current encodings for DWARF EH Items which are known to be wrong/different vs GCC are marked as TODO and will be address in follow-up patches. llvm-svn: 366326
2019-07-17 13:48:49 +00:00
# RELAX-RELOC-NEXT: 0x20 R_RISCV_ADD32 - 0x0
# RELAX-RELOC-NEXT: 0x20 R_RISCV_SUB32 - 0x0
# RELAX-RELOC-NEXT: }
# NORELAX-RELOC: Section (4) .rela.eh_frame {
# NORELAX-RELOC-NEXT: 0x1C R_RISCV_32_PCREL - 0x0
# NORELAX-RELOC-NEXT: }
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