RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity
0b8ca13018
llvm-mirror/test/CodeGen/PowerPC/f128-truncateNconv.ll

1406 lines
45 KiB
LLVM
Raw Normal View History

[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[PowerPC] Make no-PIC default to match GCC - LLVM Change the default for PowerPC LE to -fno-PIC. Differential Revision: https://reviews.llvm.org/D53383 llvm-svn: 348298
2018-12-04 21:14:57 +01:00
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
[PowerPC] Enable default support of quad precision operations Summary: Remove option guarding support of quad precision operations. Reviewers: nemanjai, #powerpc, steven.zhang Reviewed By: nemanjai, #powerpc, steven.zhang Subscribers: qiucf, wuzish, nemanjai, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D83437
2020-07-09 00:07:34 +02:00
; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck %s
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; RUN: llc -relocation-model=pic -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck %s -check-prefix=CHECK-P8
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
fp128 0xLF000000000000000400808AB851EB851,
fp128 0xL5000000000000000400E0C26324C8366,
fp128 0xL8000000000000000400A24E2E147AE14],
align 16
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2sdw(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sdw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sdw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i64
ret i64 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sdw_02(i64* nocapture %res) local_unnamed_addr #1 {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sdw_02:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sdw_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptosi fp128 %0 to i64
store i64 %conv, i64* %res, align 8
ret void
}
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2sdw_03(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sdw_03:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sdw_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i64
ret i64 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sdw_04(fp128* nocapture readonly %a,
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sdw_04:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sdw_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
fp128* nocapture readonly %b, i64* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i64
store i64 %conv, i64* %res, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @qpConv2sdw_testXForm(i64* nocapture %res, i32 signext %idx) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sdw_testXForm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: lxv v2, 32(r5)
; CHECK-NEXT: xscvqpsdz v2, v2
; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sdw_testXForm:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r4, r30, 3
; CHECK-P8-NEXT: stdx r3, r29, r4
; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptosi fp128 %0 to i64
%idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8
ret void
}
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2udw(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2udw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2udw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i64
ret i64 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw_02(i64* nocapture %res) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2udw_02:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: stxsd v2, 0(r3)
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2udw_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptoui fp128 %0 to i64
store i64 %conv, i64* %res, align 8
ret void
}
; Function Attrs: norecurse nounwind readonly
define i64 @qpConv2udw_03(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2udw_03:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: mfvsrd r3, v2
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2udw_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i64
ret i64 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw_04(fp128* nocapture readonly %a,
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2udw_04:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: stxsd v2, 0(r5)
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2udw_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: std r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
fp128* nocapture readonly %b, i64* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i64
store i64 %conv, i64* %res, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @qpConv2udw_testXForm(i64* nocapture %res, i32 signext %idx) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2udw_testXForm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sldi r4, r4, 3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: lxvx v2, 0, r5
; CHECK-NEXT: xscvqpudz v2, v2
; CHECK-NEXT: stxsdx v2, r3, r4
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2udw_testXForm:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 64
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r29, -24
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -64(r1)
; CHECK-P8-NEXT: mr r30, r4
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r29, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixunskfdi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sldi r4, r30, 3
; CHECK-P8-NEXT: stdx r3, r29, r4
; CHECK-P8-NEXT: addi r1, r1, 64
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to DW Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
2018-05-08 20:23:31 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 0), align 16
%conv = fptoui fp128 %0 to i64
%idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds i64, i64* %res, i64 %idxprom
store i64 %conv, i64* %arrayidx, align 8
ret void
}
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
; Function Attrs: norecurse nounwind readonly
define signext i32 @qpConv2sw(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sw_02(i32* nocapture %res) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sw_02:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsiwx v2, 0, r3
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sw_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptosi fp128 %0 to i32
store i32 %conv, i32* %res, align 4
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i32 @qpConv2sw_03(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sw_03:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sw_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sw_04(fp128* nocapture readonly %a,
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2sw_04:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsiwx v2, 0, r5
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2sw_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
fp128* nocapture readonly %b, i32* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i32
store i32 %conv, i32* %res, align 4
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i32 @qpConv2uw(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2uw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2uw_02(i32* nocapture %res) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2uw_02:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsiwx v2, 0, r3
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 2), align 16
%conv = fptoui fp128 %0 to i32
store i32 %conv, i32* %res, align 4
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i32 @qpConv2uw_03(fp128* nocapture readonly %a) {
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2uw_03:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array, i64 0,
i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2uw_04(fp128* nocapture readonly %a,
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-LABEL: qpConv2uw_04:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsiwx v2, 0, r5
; CHECK-NEXT: blr
;
; CHECK-P8-LABEL: qpConv2uw_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixunskfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stw r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert Quad-Precision to Word Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
2018-05-08 20:34:00 +02:00
fp128* nocapture readonly %b, i32* nocapture %res) {
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i32
store i32 %conv, i32* %res, align 4
ret void
}
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; Function Attrs: norecurse nounwind readonly
define signext i16 @qpConv2shw(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-02 18:58:27 +01:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2shw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2shw_02(i16* nocapture %res) {
; CHECK-LABEL: qpConv2shw_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2shw_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptosi fp128 %0 to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i16 @qpConv2shw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2shw_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-02 18:58:27 +01:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2shw_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2shw_04(fp128* nocapture readonly %a,
; CHECK-LABEL: qpConv2shw_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2shw_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, i16* nocapture %res) {
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i16 @qpConv2uhw(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2uhw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2uhw_02(i16* nocapture %res) {
; CHECK-LABEL: qpConv2uhw_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2uhw_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptoui fp128 %0 to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i16 @qpConv2uhw_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2uhw_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2uhw_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i16
ret i16 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2uhw_04(fp128* nocapture readonly %a,
; CHECK-LABEL: qpConv2uhw_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsihx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2uhw_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: sth r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, i16* nocapture %res) {
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i16
store i16 %conv, i16* %res, align 2
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i8 @qpConv2sb(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-02 18:58:27 +01:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2sb:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptosi fp128 %0 to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sb_02(i8* nocapture %res) {
; CHECK-LABEL: qpConv2sb_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2sb_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptosi fp128 %0 to i8
store i8 %conv, i8* %res, align 1
ret void
}
; Function Attrs: norecurse nounwind readonly
define signext i8 @qpConv2sb_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2sb_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
[DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead. The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this. Differential Revision: https://reviews.llvm.org/D56156 llvm-svn: 350235
2019-01-02 18:58:27 +01:00
; CHECK-NEXT: extsw r3, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2sb_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: extsw r3, r3
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2sb_04(fp128* nocapture readonly %a,
; CHECK-LABEL: qpConv2sb_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2sb_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, i8* nocapture %res) {
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptosi fp128 %add to i8
store i8 %conv, i8* %res, align 1
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i8 @qpConv2ub(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2ub:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%conv = fptoui fp128 %0 to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2ub_02(i8* nocapture %res) {
; CHECK-LABEL: qpConv2ub_02:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lxv v2, 32(r4)
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r3
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2ub_02:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-P8-NEXT: mr r30, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: addi r4, r4, 32
; CHECK-P8-NEXT: lvx v2, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 2), align 16
%conv = fptoui fp128 %0 to i8
store i8 %conv, i8* %res, align 1
ret void
}
; Function Attrs: norecurse nounwind readonly
define zeroext i8 @qpConv2ub_03(fp128* nocapture readonly %a) {
; CHECK-LABEL: qpConv2ub_03:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-NEXT: addis r3, r2, .LC0@toc@ha
; CHECK-NEXT: ld r3, .LC0@toc@l(r3)
; CHECK-NEXT: lxv v3, 16(r3)
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpswz v2, v2
; CHECK-NEXT: mfvsrwz r3, v2
; CHECK-NEXT: clrldi r3, r3, 32
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2ub_03:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -32(r1)
; CHECK-P8-NEXT: .cfi_def_cfa_offset 32
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: addis r4, r2, .LC0@toc@ha
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-P8-NEXT: addi r4, r4, 16
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: addi r1, r1, 32
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* getelementptr inbounds
([4 x fp128], [4 x fp128]* @f128Array,
i64 0, i64 1), align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i8
ret i8 %conv
}
; Function Attrs: norecurse nounwind
define void @qpConv2ub_04(fp128* nocapture readonly %a,
; CHECK-LABEL: qpConv2ub_04:
; CHECK: # %bb.0: # %entry
[PowerPC] [NFC] Update __float128 tests Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to the __float128 tests. Then modify the tests as required. llvm-svn: 336940
2018-07-12 22:18:57 +02:00
; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: lxv v3, 0(r4)
; CHECK-NEXT: xsaddqp v2, v2, v3
; CHECK-NEXT: xscvqpuwz v2, v2
; CHECK-NEXT: stxsibx v2, 0, r5
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
; CHECK-NEXT: blr
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
;
; CHECK-P8-LABEL: qpConv2ub_04:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
; CHECK-P8-NEXT: .cfi_def_cfa_offset 48
; CHECK-P8-NEXT: .cfi_offset lr, 16
; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r0, 16(r1)
; CHECK-P8-NEXT: stdu r1, -48(r1)
[PowerPC] Support f128 under VSX This patch is the last one in backend to support fp128 type in pre-POWER9 subtargets with VSX, removing temporary option and updating remaining tests. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D92374
2021-04-20 09:47:54 +02:00
; CHECK-P8-NEXT: lvx v2, 0, r3
; CHECK-P8-NEXT: lvx v3, 0, r4
[NFC][Test] Add test coverage for IEEE Long Double on Power8
2020-11-16 04:44:36 +01:00
; CHECK-P8-NEXT: mr r30, r5
; CHECK-P8-NEXT: bl __addkf3
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: bl __fixkfsi
; CHECK-P8-NEXT: nop
; CHECK-P8-NEXT: stb r3, 0(r30)
; CHECK-P8-NEXT: addi r1, r1, 48
; CHECK-P8-NEXT: ld r0, 16(r1)
; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P8-NEXT: mtlr r0
; CHECK-P8-NEXT: blr
fp128* nocapture readonly %b, i8* nocapture %res) {
[Power9]Legalize and emit code for truncate and convert QP to HW and Byte Legalize and emit code for truncate and convert float128 to (un)signed short and (un)signed char. Differential Revision: https://reviews.llvm.org/D46194 llvm-svn: 331797
2018-05-08 20:52:06 +02:00
entry:
%0 = load fp128, fp128* %a, align 16
%1 = load fp128, fp128* %b, align 16
%add = fadd fp128 %0, %1
%conv = fptoui fp128 %add to i8
store i8 %conv, i8* %res, align 1
ret void
}
Reference in New Issue Copy Permalink