2012-02-18 13:03:15 +01:00
|
|
|
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
|
2009-07-08 19:28:55 +02:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file contains the base ARM implementation of TargetRegisterInfo class.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2014-08-13 18:26:38 +02:00
|
|
|
#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
|
|
|
|
#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2014-03-23 00:51:00 +01:00
|
|
|
#include "MCTargetDesc/ARMBaseInfo.h"
|
2009-07-08 19:28:55 +02:00
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
2011-06-27 20:32:37 +02:00
|
|
|
|
|
|
|
#define GET_REGINFO_HEADER
|
|
|
|
#include "ARMGenRegisterInfo.inc"
|
2009-07-08 19:28:55 +02:00
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
/// Register allocation hints.
|
|
|
|
namespace ARMRI {
|
|
|
|
enum {
|
|
|
|
RegPairOdd = 1,
|
|
|
|
RegPairEven = 2
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2010-11-18 20:40:05 +01:00
|
|
|
/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
|
|
|
|
/// or a stack/pc register that we should push/pop.
|
2012-01-04 02:55:04 +01:00
|
|
|
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
|
2010-11-18 20:40:05 +01:00
|
|
|
using namespace ARM;
|
|
|
|
switch (Reg) {
|
|
|
|
case R0: case R1: case R2: case R3:
|
|
|
|
case R4: case R5: case R6: case R7:
|
|
|
|
case LR: case SP: case PC:
|
|
|
|
return true;
|
2014-02-10 15:24:23 +01:00
|
|
|
case R8: case R9: case R10: case R11: case R12:
|
2012-01-04 02:55:04 +01:00
|
|
|
// For iOS we want r7 and lr to be next to each other.
|
|
|
|
return !isIOS;
|
2010-11-18 20:40:05 +01:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-04 02:55:04 +01:00
|
|
|
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
|
2010-11-18 20:40:05 +01:00
|
|
|
using namespace ARM;
|
|
|
|
switch (Reg) {
|
2014-02-10 15:24:23 +01:00
|
|
|
case R8: case R9: case R10: case R11: case R12:
|
2012-01-04 02:55:04 +01:00
|
|
|
// iOS has this second area.
|
|
|
|
return isIOS;
|
2010-11-18 20:40:05 +01:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-04 02:55:04 +01:00
|
|
|
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
|
2010-11-18 20:40:05 +01:00
|
|
|
using namespace ARM;
|
|
|
|
switch (Reg) {
|
|
|
|
case D15: case D14: case D13: case D12:
|
|
|
|
case D11: case D10: case D9: case D8:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-01 15:16:24 +01:00
|
|
|
static inline bool isCalleeSavedRegister(unsigned Reg,
|
|
|
|
const MCPhysReg *CSRegs) {
|
|
|
|
for (unsigned i = 0; CSRegs[i]; ++i)
|
|
|
|
if (Reg == CSRegs[i])
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-07-20 23:17:29 +02:00
|
|
|
class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
|
2009-07-08 19:28:55 +02:00
|
|
|
protected:
|
2010-09-03 20:37:12 +02:00
|
|
|
/// BasePtr - ARM physical register used as a base ptr in complex stack
|
|
|
|
/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
|
|
|
|
/// variable size stack objects.
|
|
|
|
unsigned BasePtr;
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
// Can be only subclassed.
|
2015-03-12 06:12:31 +01:00
|
|
|
explicit ARMBaseRegisterInfo();
|
2009-07-08 20:31:39 +02:00
|
|
|
|
2009-07-08 22:28:28 +02:00
|
|
|
// Return the opcode that implements 'Op', or 0 if no opcode
|
|
|
|
unsigned getOpcode(int Op) const;
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
public:
|
2009-07-08 19:28:55 +02:00
|
|
|
/// Code Generation virtual methods...
|
2015-03-11 22:41:28 +01:00
|
|
|
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
|
2015-03-11 23:42:13 +01:00
|
|
|
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
|
|
|
|
CallingConv::ID) const override;
|
2012-11-07 00:05:24 +01:00
|
|
|
const uint32_t *getNoPreservedMask() const;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2013-06-27 00:27:50 +02:00
|
|
|
/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
|
|
|
|
/// case that 'returned' is on an i32 first argument if the calling convention
|
|
|
|
/// is one that can (partially) model this attribute with a preserved mask
|
|
|
|
/// (i.e. it is a calling convention that uses the same register for the first
|
|
|
|
/// i32 argument and an i32 return value)
|
|
|
|
///
|
|
|
|
/// Should return NULL in the case that the calling convention does not have
|
|
|
|
/// this property
|
2015-03-11 23:42:13 +01:00
|
|
|
const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
|
|
|
|
CallingConv::ID) const;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2014-03-10 03:09:33 +01:00
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const override;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2014-03-10 03:09:33 +01:00
|
|
|
const TargetRegisterClass *
|
|
|
|
getPointerRegClass(const MachineFunction &MF,
|
|
|
|
unsigned Kind = 0) const override;
|
|
|
|
const TargetRegisterClass *
|
|
|
|
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
|
|
|
|
|
|
|
|
const TargetRegisterClass *
|
2015-03-11 00:46:01 +01:00
|
|
|
getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
|
|
|
const MachineFunction &MF) const override;
|
2011-04-26 20:52:33 +02:00
|
|
|
|
2011-03-07 22:56:36 +01:00
|
|
|
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
2014-03-10 03:09:33 +01:00
|
|
|
MachineFunction &MF) const override;
|
2011-03-07 22:56:36 +01:00
|
|
|
|
2012-12-03 23:35:35 +01:00
|
|
|
void getRegAllocationHints(unsigned VirtReg,
|
|
|
|
ArrayRef<MCPhysReg> Order,
|
|
|
|
SmallVectorImpl<MCPhysReg> &Hints,
|
|
|
|
const MachineFunction &MF,
|
2015-07-16 00:16:00 +02:00
|
|
|
const VirtRegMap *VRM,
|
|
|
|
const LiveRegMatrix *Matrix) const override;
|
2012-12-03 23:35:35 +01:00
|
|
|
|
2015-02-24 20:10:57 +01:00
|
|
|
void updateRegAllocHint(unsigned Reg, unsigned NewReg,
|
2014-03-10 03:09:33 +01:00
|
|
|
MachineFunction &MF) const override;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2010-09-03 20:37:12 +02:00
|
|
|
bool hasBasePointer(const MachineFunction &MF) const;
|
2009-08-14 22:48:13 +02:00
|
|
|
|
Targets: commonize some stack realignment code
This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.
Multiple targets duplicated the same `needsStackRealignment` code:
- Aarch64.
- ARM.
- Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
- PowerPC.
- WebAssembly.
- x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.
The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
- AMDGPU
- BPF
- CppBackend
- MSP430
- NVPTX
- Sparc
- SystemZ
- XCore
- Out-of-tree targets
This is a breaking change! `make check` passes.
The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.
`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11160
llvm-svn: 242727
2015-07-21 00:51:32 +02:00
|
|
|
bool canRealignStack(const MachineFunction &MF) const override;
|
2014-03-10 03:09:33 +01:00
|
|
|
int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
|
|
|
|
int Idx) const override;
|
|
|
|
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
|
2010-12-18 00:09:14 +01:00
|
|
|
void materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
2010-08-20 01:52:25 +02:00
|
|
|
unsigned BaseReg, int FrameIdx,
|
2014-03-10 03:09:33 +01:00
|
|
|
int64_t Offset) const override;
|
2014-04-02 21:28:18 +02:00
|
|
|
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
|
|
|
|
int64_t Offset) const override;
|
2015-03-20 18:20:07 +01:00
|
|
|
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
|
2014-03-10 03:09:33 +01:00
|
|
|
int64_t Offset) const override;
|
2009-10-27 23:45:39 +01:00
|
|
|
|
2009-08-15 04:05:35 +02:00
|
|
|
bool cannotEliminateFrame(const MachineFunction &MF) const;
|
2009-07-08 19:28:55 +02:00
|
|
|
|
|
|
|
// Debug information queries.
|
2014-03-10 03:09:33 +01:00
|
|
|
unsigned getFrameRegister(const MachineFunction &MF) const override;
|
2010-11-15 02:45:44 +01:00
|
|
|
unsigned getBaseRegister() const { return BasePtr; }
|
2009-07-08 19:28:55 +02:00
|
|
|
|
|
|
|
bool isLowRegister(unsigned Reg) const;
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
|
|
|
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
|
|
/// specified immediate.
|
|
|
|
virtual void emitLoadConstPool(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
2014-03-10 03:09:33 +01:00
|
|
|
DebugLoc dl, unsigned DestReg, unsigned SubIdx,
|
|
|
|
int Val, ARMCC::CondCodes Pred = ARMCC::AL,
|
2011-03-05 19:43:50 +01:00
|
|
|
unsigned PredReg = 0,
|
|
|
|
unsigned MIFlags = MachineInstr::NoFlags)const;
|
2009-07-08 20:31:39 +02:00
|
|
|
|
|
|
|
/// Code Generation virtual methods...
|
2014-03-10 03:09:33 +01:00
|
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
|
2009-07-08 20:31:39 +02:00
|
|
|
|
2014-03-10 03:09:33 +01:00
|
|
|
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
|
2012-04-23 23:39:35 +02:00
|
|
|
|
2014-03-10 03:09:33 +01:00
|
|
|
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
|
2010-08-24 21:05:43 +02:00
|
|
|
|
2014-03-10 03:09:33 +01:00
|
|
|
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
|
2009-10-20 03:26:58 +02:00
|
|
|
|
2014-03-10 03:09:33 +01:00
|
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
|
|
int SPAdj, unsigned FIOperandNum,
|
2014-04-28 06:05:08 +02:00
|
|
|
RegScavenger *RS = nullptr) const override;
|
2014-07-16 22:13:31 +02:00
|
|
|
|
|
|
|
/// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
|
|
|
|
bool shouldCoalesce(MachineInstr *MI,
|
|
|
|
const TargetRegisterClass *SrcRC,
|
|
|
|
unsigned SubReg,
|
|
|
|
const TargetRegisterClass *DstRC,
|
|
|
|
unsigned DstSubReg,
|
|
|
|
const TargetRegisterClass *NewRC) const override;
|
2009-07-08 19:28:55 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
} // end namespace llvm
|
|
|
|
|
|
|
|
#endif
|