2012-12-11 22:25:42 +01:00
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//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H
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#define LLVM_LIB_TARGET_R600_SIISELLOWERING_H
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2012-12-11 22:25:42 +01:00
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#include "AMDGPUISelLowering.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class SITargetLowering : public AMDGPUTargetLowering {
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2013-10-23 02:44:32 +02:00
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SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
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2014-04-11 22:59:54 +02:00
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SDValue Chain, unsigned Offset, bool Signed) const;
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2013-08-15 01:24:45 +02:00
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SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
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SelectionDAG &DAG) const;
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2014-07-21 16:01:14 +02:00
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const override;
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2014-07-26 08:23:37 +02:00
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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2014-07-21 17:45:01 +02:00
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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2013-11-14 00:36:50 +01:00
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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2014-02-04 18:18:40 +01:00
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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2014-07-16 01:50:10 +02:00
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SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const;
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2014-07-15 22:18:31 +02:00
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SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
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2013-11-14 00:36:50 +01:00
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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2014-07-19 20:44:39 +02:00
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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2012-12-19 23:10:31 +01:00
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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2012-12-11 22:25:42 +01:00
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2013-02-26 18:52:23 +01:00
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bool foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const;
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2013-08-07 01:08:18 +02:00
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const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
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const SDValue &Op) const;
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2013-05-20 17:02:01 +02:00
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bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const;
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2013-05-18 02:21:46 +02:00
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void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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2013-02-26 18:52:23 +01:00
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unsigned RegClass, bool &ScalarSlotUsed) const;
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2014-09-17 17:35:43 +02:00
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SDNode *legalizeOperands(MachineSDNode *N, SelectionDAG &DAG) const;
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2013-04-10 10:39:08 +02:00
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void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
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2013-06-03 19:39:58 +02:00
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MachineSDNode *AdjustRegClass(MachineSDNode *N, SelectionDAG &DAG) const;
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2013-04-10 10:39:08 +02:00
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2014-06-11 19:50:44 +02:00
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static SDValue performUCharToFloatCombine(SDNode *N,
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DAGCombinerInfo &DCI);
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2014-08-15 19:49:05 +02:00
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SDValue performSHLPtrCombine(SDNode *N,
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unsigned AS,
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DAGCombinerInfo &DCI) const;
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2014-06-11 19:50:44 +02:00
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2012-12-11 22:25:42 +01:00
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public:
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SITargetLowering(TargetMachine &tm);
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2014-08-15 19:17:07 +02:00
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bool isLegalAddressingMode(const AddrMode &AM,
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Type *Ty) const override;
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2014-07-27 19:46:40 +02:00
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
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unsigned Align,
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bool *IsFast) const override;
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2014-07-03 02:23:43 +02:00
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2014-07-28 19:49:26 +02:00
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset,
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bool ZeroMemset,
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bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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2014-07-03 02:23:43 +02:00
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(EVT VT) const override;
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2013-03-07 10:03:52 +01:00
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2014-04-29 09:57:24 +02:00
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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2014-03-31 21:54:27 +02:00
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2013-03-07 10:03:52 +01:00
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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2013-05-25 04:42:55 +02:00
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SDLoc DL, SelectionDAG &DAG,
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2014-04-29 09:57:24 +02:00
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SmallVectorImpl<SDValue> &InVals) const override;
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2013-03-07 10:03:52 +01:00
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2014-04-29 09:57:24 +02:00
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MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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MachineBasicBlock * BB) const override;
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EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
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MVT getScalarShiftAmountTy(EVT VT) const override;
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
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void AdjustInstrPostInstrSelection(MachineInstr *MI,
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SDNode *Node) const override;
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2013-02-26 18:52:23 +01:00
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int32_t analyzeImmediate(const SDNode *N) const;
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2013-06-03 19:40:18 +02:00
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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2014-04-29 09:57:24 +02:00
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unsigned Reg, EVT VT) const override;
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2012-12-11 22:25:42 +01:00
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};
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} // End namespace llvm
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2014-08-13 18:26:38 +02:00
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#endif
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