llvm-mirror/test/CodeGen/ARM/str_pre-2.ll

; RUN: llc < %s -mtriple=armv6-linux-gnu | FileCheck %s

@b = external global i64*

define i64 @t(i64 %a) nounwind readonly {
entry:
; CHECK: str lr, [sp, #-4]!
; CHECK: ldr lr, [sp], #4
	%0 = load i64** @b, align 4
	%1 = load i64* %0, align 4
	%2 = mul i64 %1, %a
	ret i64 %2
}
Update the test llvm-svn: 122666 2011-01-01 21:57:26 +01:00			`; RUN: llc < %s -mtriple=armv6-linux-gnu \| FileCheck %s`
Fold preceding / trailing base inc / dec into the single load / store as well. llvm-svn: 72756 2009-06-03 08:14:58 +02:00
			`@b = external global i64*`

			`define i64 @t(i64 %a) nounwind readonly {`
			`entry:`
ARM stm/ldm instructions require more than one register in the register list. Otherwise, a plain str/ldr should be used instead. Make sure we account for that in prologue/epilogue code generation. rdar://8745460 llvm-svn: 121391 2010-12-09 19:31:13 +01:00			`; CHECK: str lr, [sp, #-4]!`
			`; CHECK: ldr lr, [sp], #4`
Fold preceding / trailing base inc / dec into the single load / store as well. llvm-svn: 72756 2009-06-03 08:14:58 +02:00			`%0 = load i64** @b, align 4`
			`%1 = load i64* %0, align 4`
			`%2 = mul i64 %1, %a`
			`ret i64 %2`
			`}`