2012-02-18 13:03:15 +01:00
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//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2012-02-18 13:03:15 +01:00
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//
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2006-02-05 06:50:24 +01:00
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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2008-11-24 08:34:46 +01:00
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include "llvm/Target/Target.td"
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2006-02-05 06:50:24 +01:00
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//===----------------------------------------------------------------------===//
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// SPARC Subtarget features.
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//
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2013-06-04 20:33:25 +02:00
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2017-07-18 21:08:38 +02:00
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def FeatureSoftMulDiv
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: SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true",
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"Use software emulation for integer multiply and divide">;
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2017-07-20 22:09:11 +02:00
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def FeatureNoFSMULD
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: SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true",
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"Disable the fsmuld instruction.">;
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def FeatureNoFMULS
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: SubtargetFeature<"no-fmuls", "HasNoFMULS", "true",
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"Disable the fmuls instruction.">;
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2006-02-05 06:50:24 +01:00
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def FeatureV9
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"v9", "IsV9", "true",
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"Enable SPARC-V9 instructions">;
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2006-02-05 06:50:24 +01:00
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def FeatureV8Deprecated
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
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"Enable deprecated V8 instructions in V9 mode">;
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2006-02-05 06:50:24 +01:00
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def FeatureVIS
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"vis", "IsVIS", "true",
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"Enable UltraSPARC Visual Instruction Set extensions">;
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2014-03-02 20:31:21 +01:00
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def FeatureVIS2
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"vis2", "IsVIS2", "true",
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"Enable Visual Instruction Set extensions II">;
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2014-03-02 20:31:21 +01:00
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def FeatureVIS3
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"vis3", "IsVIS3", "true",
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"Enable Visual Instruction Set extensions III">;
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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def FeatureLeon
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"leon", "IsLeon", "true",
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"Enable LEON extensions">;
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2018-09-27 14:34:48 +02:00
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def FeaturePWRPSR
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: SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true",
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"Enable the PWRPSR instruction">;
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2006-02-05 06:50:24 +01:00
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2013-08-25 20:30:06 +02:00
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def FeatureHardQuad
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2016-08-12 16:48:09 +02:00
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: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
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"Enable quad-word floating point instructions">;
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2013-08-25 20:30:06 +02:00
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2014-01-26 07:09:59 +01:00
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def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
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"Use the popc (population count) instruction">;
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2016-08-12 16:48:09 +02:00
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def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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2017-07-20 22:09:11 +02:00
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"Use software emulation for floating point">;
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2016-05-18 11:14:13 +02:00
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2017-07-20 22:09:11 +02:00
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//==== Features added predmoninantly for LEON subtarget support
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2016-05-09 13:55:15 +02:00
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include "LeonFeatures.td"
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2006-02-05 06:50:24 +01:00
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//===----------------------------------------------------------------------===//
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2008-03-17 06:41:48 +01:00
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// Register File, Calling Conv, Instruction Descriptions
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2006-02-05 06:50:24 +01:00
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//===----------------------------------------------------------------------===//
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include "SparcRegisterInfo.td"
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2008-03-17 06:41:48 +01:00
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include "SparcCallingConv.td"
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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include "SparcSchedule.td"
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2006-02-05 06:50:24 +01:00
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include "SparcInstrInfo.td"
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2010-04-05 05:10:20 +02:00
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def SparcInstrInfo : InstrInfo;
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2006-02-05 06:50:24 +01:00
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2016-08-12 16:48:09 +02:00
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def SparcAsmParser : AsmParser {
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bit ShouldEmitMatchRegisterName = 0;
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}
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2014-01-04 12:30:13 +01:00
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2006-02-05 06:50:24 +01:00
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//===----------------------------------------------------------------------===//
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// SPARC processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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2016-08-12 16:48:09 +02:00
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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2017-07-20 22:09:11 +02:00
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def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>;
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2016-08-12 16:48:09 +02:00
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def : Proc<"v8", []>;
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def : Proc<"supersparc", []>;
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def : Proc<"sparclite", []>;
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def : Proc<"f934", []>;
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def : Proc<"hypersparc", []>;
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def : Proc<"sparclite86x", []>;
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def : Proc<"sparclet", []>;
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def : Proc<"tsc701", []>;
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2016-09-13 19:51:41 +02:00
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def : Proc<"myriad2", [FeatureLeon, LeonCASA]>;
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def : Proc<"myriad2.1", [FeatureLeon, LeonCASA]>;
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def : Proc<"myriad2.2", [FeatureLeon, LeonCASA]>;
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2017-10-02 20:50:48 +02:00
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def : Proc<"myriad2.3", [FeatureLeon, LeonCASA]>;
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2016-09-13 19:51:41 +02:00
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def : Proc<"ma2100", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2150", [FeatureLeon, LeonCASA]>;
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2017-10-02 20:50:48 +02:00
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def : Proc<"ma2155", [FeatureLeon, LeonCASA]>;
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2016-09-13 19:51:41 +02:00
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def : Proc<"ma2450", [FeatureLeon, LeonCASA]>;
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2017-10-02 20:50:48 +02:00
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def : Proc<"ma2455", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2x5x", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2080", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2085", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2480", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2485", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>;
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2016-08-12 16:48:09 +02:00
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def : Proc<"v9", [FeatureV9]>;
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def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
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def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
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FeatureVIS2]>;
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def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
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FeatureVIS2]>;
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def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2]>;
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def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2]>;
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def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2, FeatureVIS3]>;
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2006-02-05 06:50:24 +01:00
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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// LEON 2 FT generic
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2016-08-12 16:48:09 +02:00
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def : Processor<"leon2", LEON2Itineraries,
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[FeatureLeon]>;
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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// LEON 2 FT (AT697E)
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2016-08-12 16:48:09 +02:00
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// TO DO: Place-holder: Processor specific features will be added *very* soon here.
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def : Processor<"at697e", LEON2Itineraries,
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2018-04-20 09:53:27 +02:00
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[FeatureLeon, InsertNOPLoad]>;
|
[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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// LEON 2 FT (AT697F)
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2016-08-12 16:48:09 +02:00
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// TO DO: Place-holder: Processor specific features will be added *very* soon here.
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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def : Processor<"at697f", LEON2Itineraries,
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2016-08-12 16:48:09 +02:00
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[FeatureLeon, InsertNOPLoad]>;
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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// LEON 3 FT generic
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2016-08-12 16:48:09 +02:00
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def : Processor<"leon3", LEON3Itineraries,
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[FeatureLeon, UMACSMACSupport]>;
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[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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2016-05-16 13:02:00 +02:00
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// LEON 3 FT (UT699). Provides features for the UT699 processor
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2016-08-12 16:48:09 +02:00
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// - covers all the erratum fixes for LEON3, but does not support the CASA instruction.
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2017-07-20 22:09:11 +02:00
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def : Processor<"ut699", LEON3Itineraries,
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[FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>;
|
[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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2016-05-16 13:02:00 +02:00
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// LEON3 FT (GR712RC). Provides features for the GR712RC processor.
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2016-08-12 16:48:09 +02:00
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// - covers all the erratum fixed for LEON3 and support for the CASA instruction.
|
[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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def : Processor<"gr712rc", LEON3Itineraries,
|
2016-08-12 16:48:09 +02:00
|
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[FeatureLeon, LeonCASA]>;
|
[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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// LEON 4 FT generic
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def : Processor<"leon4", LEON4Itineraries,
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2016-08-12 16:48:09 +02:00
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|
[FeatureLeon, UMACSMACSupport, LeonCASA]>;
|
[Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.
The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.
As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.
Phabricator Review: http://reviews.llvm.org/D19359
llvm-svn: 267121
2016-04-22 10:17:17 +02:00
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2016-08-12 16:48:09 +02:00
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// LEON 4 FT (GR740)
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// TO DO: Place-holder: Processor specific features will be added *very* soon here.
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def : Processor<"gr740", LEON4Itineraries,
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2018-09-27 14:34:48 +02:00
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[FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter,
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FeaturePWRPSR]>;
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2006-02-05 06:50:24 +01:00
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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2015-03-28 05:03:51 +01:00
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def SparcAsmWriter : AsmWriter {
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2016-08-12 16:48:09 +02:00
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string AsmWriterClassName = "InstPrinter";
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2015-03-28 05:03:51 +01:00
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int PassSubtarget = 1;
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int Variant = 0;
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}
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2006-02-05 06:50:24 +01:00
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def Sparc : Target {
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// Pull in Instruction Info:
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let InstructionSet = SparcInstrInfo;
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2016-08-12 16:48:09 +02:00
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let AssemblyParsers = [SparcAsmParser];
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let AssemblyWriters = [SparcAsmWriter];
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[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
llvm-svn: 325931
2018-02-23 19:25:08 +01:00
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let AllowRegisterRenaming = 1;
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2006-02-05 06:50:24 +01:00
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}
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