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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
184 lines
7.3 KiB
TableGen
184 lines
7.3 KiB
TableGen
//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SPARC Subtarget features.
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//
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def FeatureSoftMulDiv
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: SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true",
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"Use software emulation for integer multiply and divide">;
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def FeatureNoFSMULD
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: SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true",
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"Disable the fsmuld instruction.">;
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def FeatureNoFMULS
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: SubtargetFeature<"no-fmuls", "HasNoFMULS", "true",
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"Disable the fmuls instruction.">;
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def FeatureV9
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: SubtargetFeature<"v9", "IsV9", "true",
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"Enable SPARC-V9 instructions">;
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def FeatureV8Deprecated
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: SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
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"Enable deprecated V8 instructions in V9 mode">;
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def FeatureVIS
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: SubtargetFeature<"vis", "IsVIS", "true",
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"Enable UltraSPARC Visual Instruction Set extensions">;
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def FeatureVIS2
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: SubtargetFeature<"vis2", "IsVIS2", "true",
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"Enable Visual Instruction Set extensions II">;
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def FeatureVIS3
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: SubtargetFeature<"vis3", "IsVIS3", "true",
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"Enable Visual Instruction Set extensions III">;
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def FeatureLeon
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: SubtargetFeature<"leon", "IsLeon", "true",
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"Enable LEON extensions">;
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def FeaturePWRPSR
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: SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true",
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"Enable the PWRPSR instruction">;
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def FeatureHardQuad
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: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
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"Enable quad-word floating point instructions">;
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def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
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"Use the popc (population count) instruction">;
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def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
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"Use software emulation for floating point">;
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//==== Features added predmoninantly for LEON subtarget support
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include "LeonFeatures.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "SparcRegisterInfo.td"
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include "SparcCallingConv.td"
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include "SparcSchedule.td"
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include "SparcInstrInfo.td"
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def SparcInstrInfo : InstrInfo;
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def SparcAsmParser : AsmParser {
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bit ShouldEmitMatchRegisterName = 0;
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}
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//===----------------------------------------------------------------------===//
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// SPARC processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>;
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def : Proc<"v8", []>;
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def : Proc<"supersparc", []>;
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def : Proc<"sparclite", []>;
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def : Proc<"f934", []>;
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def : Proc<"hypersparc", []>;
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def : Proc<"sparclite86x", []>;
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def : Proc<"sparclet", []>;
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def : Proc<"tsc701", []>;
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def : Proc<"myriad2", [FeatureLeon, LeonCASA]>;
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def : Proc<"myriad2.1", [FeatureLeon, LeonCASA]>;
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def : Proc<"myriad2.2", [FeatureLeon, LeonCASA]>;
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def : Proc<"myriad2.3", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2100", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2150", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2155", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2450", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2455", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2x5x", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2080", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2085", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2480", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2485", [FeatureLeon, LeonCASA]>;
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def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>;
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def : Proc<"v9", [FeatureV9]>;
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def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
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def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
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FeatureVIS2]>;
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def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
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FeatureVIS2]>;
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def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2]>;
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def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2]>;
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def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2, FeatureVIS3]>;
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// LEON 2 FT generic
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def : Processor<"leon2", LEON2Itineraries,
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[FeatureLeon]>;
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// LEON 2 FT (AT697E)
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// TO DO: Place-holder: Processor specific features will be added *very* soon here.
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def : Processor<"at697e", LEON2Itineraries,
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[FeatureLeon, InsertNOPLoad]>;
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// LEON 2 FT (AT697F)
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// TO DO: Place-holder: Processor specific features will be added *very* soon here.
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def : Processor<"at697f", LEON2Itineraries,
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[FeatureLeon, InsertNOPLoad]>;
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// LEON 3 FT generic
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def : Processor<"leon3", LEON3Itineraries,
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[FeatureLeon, UMACSMACSupport]>;
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// LEON 3 FT (UT699). Provides features for the UT699 processor
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// - covers all the erratum fixes for LEON3, but does not support the CASA instruction.
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def : Processor<"ut699", LEON3Itineraries,
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[FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>;
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// LEON3 FT (GR712RC). Provides features for the GR712RC processor.
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// - covers all the erratum fixed for LEON3 and support for the CASA instruction.
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def : Processor<"gr712rc", LEON3Itineraries,
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[FeatureLeon, LeonCASA]>;
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// LEON 4 FT generic
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def : Processor<"leon4", LEON4Itineraries,
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[FeatureLeon, UMACSMACSupport, LeonCASA]>;
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// LEON 4 FT (GR740)
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// TO DO: Place-holder: Processor specific features will be added *very* soon here.
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def : Processor<"gr740", LEON4Itineraries,
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[FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter,
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FeaturePWRPSR]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def SparcAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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}
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def Sparc : Target {
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// Pull in Instruction Info:
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let InstructionSet = SparcInstrInfo;
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let AssemblyParsers = [SparcAsmParser];
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let AssemblyWriters = [SparcAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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