llvm-mirror/test/CodeGen/X86/pr43507.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s

define <8 x i1> @ham(i64 %arg) {
; CHECK-LABEL: ham:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    testb $1, %dil
; CHECK-NEXT:    movl $255, %ecx
; CHECK-NEXT:    cmovel %eax, %ecx
; CHECK-NEXT:    kmovd %ecx, %k0
; CHECK-NEXT:    vpmovm2w %k0, %xmm0
; CHECK-NEXT:    retq
  %tmp = trunc i64 %arg to i1
  %tmp1 = insertelement <8 x i1> undef, i1 %tmp, i32 0
  %tmp2 = shufflevector <8 x i1> %tmp1, <8 x i1> undef, <8 x i32> zeroinitializer
  ret <8 x i1> %tmp2
}
[X86] Mask off upper bits of splat element in LowerBUILD_VECTORvXi1 when forming a SELECT. The i1 scalar would have been type legalized to i8, but that doesn't guarantee anything about the upper bits. If we're going to use it as condition we need to make sure the upper bits are 0. I've special cased ISD::SETCC conditions since that should guarantee zero upper bits. We could go further and use computeKnownBits, but we have no tests that would need that. Fixes PR43507. llvm-svn: 373246 2019-09-30 20:43:44 +02:00			`; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py`
			`; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx \| FileCheck %s`

			`define <8 x i1> @ham(i64 %arg) {`
			`; CHECK-LABEL: ham:`
			`; CHECK: # %bb.0:`
			`; CHECK-NEXT: xorl %eax, %eax`
			`; CHECK-NEXT: testb $1, %dil`
			`; CHECK-NEXT: movl $255, %ecx`
			`; CHECK-NEXT: cmovel %eax, %ecx`
			`; CHECK-NEXT: kmovd %ecx, %k0`
			`; CHECK-NEXT: vpmovm2w %k0, %xmm0`
			`; CHECK-NEXT: retq`
			`%tmp = trunc i64 %arg to i1`
			`%tmp1 = insertelement <8 x i1> undef, i1 %tmp, i32 0`
			`%tmp2 = shufflevector <8 x i1> %tmp1, <8 x i1> undef, <8 x i32> zeroinitializer`
			`ret <8 x i1> %tmp2`
			`}`