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760e938aa1
The i1 scalar would have been type legalized to i8, but that doesn't guarantee anything about the upper bits. If we're going to use it as condition we need to make sure the upper bits are 0. I've special cased ISD::SETCC conditions since that should guarantee zero upper bits. We could go further and use computeKnownBits, but we have no tests that would need that. Fixes PR43507. llvm-svn: 373246
19 lines
644 B
LLVM
19 lines
644 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s
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define <8 x i1> @ham(i64 %arg) {
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; CHECK-LABEL: ham:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: movl $255, %ecx
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; CHECK-NEXT: cmovel %eax, %ecx
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; CHECK-NEXT: kmovd %ecx, %k0
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; CHECK-NEXT: vpmovm2w %k0, %xmm0
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; CHECK-NEXT: retq
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%tmp = trunc i64 %arg to i1
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%tmp1 = insertelement <8 x i1> undef, i1 %tmp, i32 0
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%tmp2 = shufflevector <8 x i1> %tmp1, <8 x i1> undef, <8 x i32> zeroinitializer
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ret <8 x i1> %tmp2
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}
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