llvm-mirror/test/CodeGen/MSP430/asm-clobbers.ll

; RUN: llc < %s | FileCheck %s

target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"
target triple = "msp430---elf"

define void @test() {
entry:
; CHECK-LABEL: test:
; CHECK: push r10
  call void asm sideeffect "", "~{r10}"()
; CHECK: pop r10
  ret void
}
Drop the W postfix on the 16-bit registers. This ensures the inline assembly register constraints are properly recognised in TargetLowering::getRegForInlineAsmConstraint. llvm-svn: 217479 2014-09-10 08:58:14 +02:00			`; RUN: llc < %s \| FileCheck %s`

			`target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"`
			`target triple = "msp430---elf"`

			`define void @test() {`
			`entry:`
			`; CHECK-LABEL: test:`
[MSP430] Add MC layer Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948 2018-11-15 13:29:43 +01:00			`; CHECK: push r10`
Drop the W postfix on the 16-bit registers. This ensures the inline assembly register constraints are properly recognised in TargetLowering::getRegForInlineAsmConstraint. llvm-svn: 217479 2014-09-10 08:58:14 +02:00			`call void asm sideeffect "", "~{r10}"()`
[MSP430] Add MC layer Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948 2018-11-15 13:29:43 +01:00			`; CHECK: pop r10`
Drop the W postfix on the 16-bit registers. This ensures the inline assembly register constraints are properly recognised in TargetLowering::getRegForInlineAsmConstraint. llvm-svn: 217479 2014-09-10 08:58:14 +02:00			`ret void`
			`}`