QingShan Zhang 2f3956c41c [Power9] Enable the Out-of-Order scheduling model for P9 hw ... When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285		2019-01-03 05:04:18 +00:00
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AArch64	Reversing the commit in revision 350186. Revision causes regression in 4	2019-01-01 07:28:55 +00:00
AMDGPU	[AMDGPU] Handle OR as operand of raw load/store	2019-01-02 09:47:41 +00:00
ARC
ARM
AVR
BPF
Generic
Hexagon	[DAGCombiner] allow narrowing of add followed by truncate	2018-12-22 17:10:31 +00:00
Inputs
Lanai
Mips	[MIPS GlobalISel] Select G_SELECT	2018-12-25 14:42:30 +00:00
MIR
MSP430
Nios2
NVPTX	[NVPTX] Allow libcalls that are defined in the current module.	2018-12-26 19:12:31 +00:00
PowerPC	[Power9] Enable the Out-of-Order scheduling model for P9 hw	2019-01-03 05:04:18 +00:00
RISCV
SPARC
SystemZ
Thumb
Thumb2
WebAssembly	[WebAssembly][NFC] Elaborate on simd-noopt test comment	2019-01-02 20:43:08 +00:00
WinCFGuard
WinEH
X86	[X86] Add load folding support to the custom isel we do for X86ISD::UMUL/SMUL.	2019-01-02 23:24:08 +00:00
XCore