llvm-mirror/test/CodeGen/MSP430/select-use-sr.ll

; RUN: llc < %s -march=msp430 | FileCheck %s
; PR32769

target triple = "msp430"

; Test that CMP instruction is not removed by MachineCSE.
;
; CHECK-LABEL: @f
; CHECK: cmp r15, r13
; CHECK: cmp r15, r13
; CHECK-NEXT: jeq .LBB0_2
define i16 @f(i16, i16, i16, i16) {
entry:
  %4 = icmp ult i16 %1, %3
  %5 = zext i1 %4 to i16
  %6 = icmp ult i16 %0, %2
  %7 = zext i1 %6 to i16
  %8 = icmp eq i16 %1, %3
  %out = select i1 %8, i16 %5, i16 %7
  ret i16 %out
}
[MSP430] Fix PR32769: Select8 and Select16 need to have SR in Uses. If Select pseudo instruction doesn't have use SR, then CMP instructions are being marked as dead and later can be removed by MachineCSE pass. This leads to incorrect code generation. Differential Revision: https://reviews.llvm.org/D32473 llvm-svn: 301372 2017-04-26 02:33:59 +02:00			`; RUN: llc < %s -march=msp430 \| FileCheck %s`
			`; PR32769`

			`target triple = "msp430"`

			`; Test that CMP instruction is not removed by MachineCSE.`
			`;`
			`; CHECK-LABEL: @f`
[MSP430] Add MC layer Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948 2018-11-15 13:29:43 +01:00			`; CHECK: cmp r15, r13`
			`; CHECK: cmp r15, r13`
[MSP430] Fix PR32769: Select8 and Select16 need to have SR in Uses. If Select pseudo instruction doesn't have use SR, then CMP instructions are being marked as dead and later can be removed by MachineCSE pass. This leads to incorrect code generation. Differential Revision: https://reviews.llvm.org/D32473 llvm-svn: 301372 2017-04-26 02:33:59 +02:00			`; CHECK-NEXT: jeq .LBB0_2`
			`define i16 @f(i16, i16, i16, i16) {`
			`entry:`
			`%4 = icmp ult i16 %1, %3`
			`%5 = zext i1 %4 to i16`
			`%6 = icmp ult i16 %0, %2`
			`%7 = zext i1 %6 to i16`
			`%8 = icmp eq i16 %1, %3`
			`%out = select i1 %8, i16 %5, i16 %7`
			`ret i16 %out`
			`}`