2012-02-28 08:46:26 +01:00
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//===-- MipsRegisterInfo.h - Mips Register Information Impl -----*- C++ -*-===//
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2007-06-06 09:42:06 +02:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 09:42:06 +02:00
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//
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-06-06 09:42:06 +02:00
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//
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2008-02-10 19:45:23 +01:00
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// This file contains the Mips implementation of the TargetRegisterInfo class.
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2007-06-06 09:42:06 +02:00
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//
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-06-06 09:42:06 +02:00
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2014-08-13 18:26:38 +02:00
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H
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2007-06-06 09:42:06 +02:00
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2008-07-14 16:42:54 +02:00
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#include "Mips.h"
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2008-02-10 19:45:23 +01:00
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#include "llvm/Target/TargetRegisterInfo.h"
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2011-06-27 20:32:37 +02:00
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#define GET_REGINFO_HEADER
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#include "MipsGenRegisterInfo.inc"
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2007-06-06 09:42:06 +02:00
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namespace llvm {
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2012-08-01 01:41:32 +02:00
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class MipsRegisterInfo : public MipsGenRegisterInfo {
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public:
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2016-05-09 15:38:25 +02:00
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enum class MipsPtrClass {
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/// The default register class for integer values.
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Default = 0,
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/// The subset of registers permitted in certain microMIPS instructions
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/// such as lw16.
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GPR16MM = 1,
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/// The stack pointer only.
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StackPointer = 2,
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/// The global pointer only.
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GlobalPointer = 3,
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};
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2015-03-12 06:43:57 +01:00
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MipsRegisterInfo();
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2007-06-06 09:42:06 +02:00
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2008-07-14 16:42:54 +02:00
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/// Get PIC indirect call register
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2009-08-13 00:10:57 +02:00
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static unsigned getPICCallReg();
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2008-07-14 16:42:54 +02:00
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2007-06-06 09:42:06 +02:00
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/// Code Generation virtual methods...
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2013-08-20 23:08:22 +02:00
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const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
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2014-04-29 09:58:02 +02:00
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unsigned Kind) const override;
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2013-08-20 23:08:22 +02:00
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2013-01-22 22:34:25 +01:00
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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2014-04-29 09:58:02 +02:00
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MachineFunction &MF) const override;
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2015-03-11 22:41:28 +01:00
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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2015-03-11 23:42:13 +01:00
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 00:25:39 +02:00
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static const uint32_t *getMips16RetHelperMask();
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2007-06-06 09:42:06 +02:00
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2014-04-29 09:58:02 +02:00
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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2007-06-06 09:42:06 +02:00
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2014-04-29 09:58:02 +02:00
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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2012-03-28 02:24:17 +02:00
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2014-04-29 09:58:02 +02:00
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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2012-04-23 23:39:35 +02:00
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2007-08-28 07:13:42 +02:00
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/// Stack Frame Processing Methods
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2010-08-27 01:32:16 +02:00
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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2013-01-31 21:02:54 +01:00
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int SPAdj, unsigned FIOperandNum,
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2014-04-29 09:58:02 +02:00
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RegScavenger *RS = nullptr) const override;
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2007-06-06 09:42:06 +02:00
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2015-06-02 15:14:46 +02:00
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// Stack realignment queries.
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Targets: commonize some stack realignment code
This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.
Multiple targets duplicated the same `needsStackRealignment` code:
- Aarch64.
- ARM.
- Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
- PowerPC.
- WebAssembly.
- x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.
The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
- AMDGPU
- BPF
- CppBackend
- MSP430
- NVPTX
- Sparc
- SystemZ
- XCore
- Out-of-tree targets
This is a breaking change! `make check` passes.
The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.
`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11160
llvm-svn: 242727
2015-07-21 00:51:32 +02:00
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bool canRealignStack(const MachineFunction &MF) const override;
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2015-06-02 15:14:46 +02:00
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2007-08-28 07:13:42 +02:00
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/// Debug information queries.
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2014-04-29 09:58:02 +02:00
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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2007-06-06 09:42:06 +02:00
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2013-03-29 20:17:42 +01:00
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/// \brief Return GPR register class.
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virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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2012-08-01 01:41:32 +02:00
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private:
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virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
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int FrameIndex, uint64_t StackSize,
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int64_t SPOffset) const = 0;
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2007-06-06 09:42:06 +02:00
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};
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} // end namespace llvm
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#endif
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