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llvm-mirror/test/DebugInfo/AMDGPU/print-reg-name.s

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[AMDGPU] Implement wave64 DWARF register mapping Summary: Implement the DWARF register mapping described in llvm/docs/AMDGPUUsage.rst This is currently limited to wave64 VGPRs/AGPRs. This also includes some minor changes in AMDGPUInstPrinter, AMDGPUMCTargetDesc, and AMDGPUAsmParser to make generating CFI assembly text and ELF sections possible to ease testing, although complete CFI support is not yet implemented. Tags: #llvm Differential Revision: https://reviews.llvm.org/D74915
2019-11-08 21:07:54 +01:00
; RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm %s | FileCheck %s
[AMDGPU] Print DWARF register numbers in AMDGPUInstPrinter Summary: Explanation is in a comment in the diff, but essentially printing a physical register name here is ambiguous. Until we can implement printing a DWARF register name here just use the encoding directly. Tags: #llvm Differential Revision: https://reviews.llvm.org/D76253
2020-03-16 22:12:09 +01:00
; FIXME: Currently we can't print register names in CFI directives
; without extending MC to support DWARF register names that are distinct
; from physical register names.
[AMDGPU] Implement wave64 DWARF register mapping Summary: Implement the DWARF register mapping described in llvm/docs/AMDGPUUsage.rst This is currently limited to wave64 VGPRs/AGPRs. This also includes some minor changes in AMDGPUInstPrinter, AMDGPUMCTargetDesc, and AMDGPUAsmParser to make generating CFI assembly text and ELF sections possible to ease testing, although complete CFI support is not yet implemented. Tags: #llvm Differential Revision: https://reviews.llvm.org/D74915
2019-11-08 21:07:54 +01:00
.text
f:
.cfi_startproc
[AMDGPU] Print DWARF register numbers in AMDGPUInstPrinter Summary: Explanation is in a comment in the diff, but essentially printing a physical register name here is ambiguous. Until we can implement printing a DWARF register name here just use the encoding directly. Tags: #llvm Differential Revision: https://reviews.llvm.org/D76253
2020-03-16 22:12:09 +01:00
; CHECK: .cfi_undefined 2560
.cfi_undefined 2560
; FIXME: Until we implement a distinct set of DWARF register names we
; will continue to parse physical registers and pick an arbitrary encoding.
; CHECK: .cfi_undefined 2560
.cfi_undefined v0
[AMDGPU] Implement wave64 DWARF register mapping Summary: Implement the DWARF register mapping described in llvm/docs/AMDGPUUsage.rst This is currently limited to wave64 VGPRs/AGPRs. This also includes some minor changes in AMDGPUInstPrinter, AMDGPUMCTargetDesc, and AMDGPUAsmParser to make generating CFI assembly text and ELF sections possible to ease testing, although complete CFI support is not yet implemented. Tags: #llvm Differential Revision: https://reviews.llvm.org/D74915
2019-11-08 21:07:54 +01:00
.cfi_endproc
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