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llvm-mirror/test/CodeGen/ARM/sadd_sat.ll

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Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC llvm-svn: 375401
2019-10-21 11:43:37 +02:00
; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
[ARM] Only produce qadd8b under hasV6Ops When compiling for a arm5te cpu from clang, the +dsp attribute is set. This meant we could try and generate qadd8 instructions where we would end up having no pattern. I've changed the condition here to be hasV6Ops && hasDSP, which is what other parts of ARMISelLowering seem to use for similar instructions. Fixed PR45677. Differential Revision: https://reviews.llvm.org/D78877
2020-04-26 22:58:58 +02:00
; RUN: llc < %s -mtriple=armv5te-none-eabi -mattr=+dsp | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC llvm-svn: 375401
2019-10-21 11:43:37 +02:00
; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
declare i4 @llvm.sadd.sat.i4(i4, i4)
declare i8 @llvm.sadd.sat.i8(i8, i8)
declare i16 @llvm.sadd.sat.i16(i16, i16)
declare i32 @llvm.sadd.sat.i32(i32, i32)
declare i64 @llvm.sadd.sat.i64(i64, i64)
define i32 @func(i32 %x, i32 %y) nounwind {
; CHECK-T1-LABEL: func:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: mov r2, r0
; CHECK-T1-NEXT: movs r3, #1
; CHECK-T1-NEXT: adds r0, r0, r1
; CHECK-T1-NEXT: mov r1, r3
; CHECK-T1-NEXT: bmi .LBB0_2
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: movs r1, #0
; CHECK-T1-NEXT: .LBB0_2:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bne .LBB0_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: lsls r1, r3, #31
; CHECK-T1-NEXT: cmp r0, r2
; CHECK-T1-NEXT: bvs .LBB0_5
; CHECK-T1-NEXT: b .LBB0_6
; CHECK-T1-NEXT: .LBB0_4:
; CHECK-T1-NEXT: ldr r1, .LCPI0_0
; CHECK-T1-NEXT: cmp r0, r2
; CHECK-T1-NEXT: bvc .LBB0_6
; CHECK-T1-NEXT: .LBB0_5:
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: .LBB0_6:
; CHECK-T1-NEXT: bx lr
; CHECK-T1-NEXT: .p2align 2
; CHECK-T1-NEXT: @ %bb.7:
; CHECK-T1-NEXT: .LCPI0_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
;
[ARM] Add qadd lowering from a sadd_sat This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
2019-10-21 14:33:46 +02:00
; CHECK-T2NODSP-LABEL: func:
; CHECK-T2NODSP: @ %bb.0:
; CHECK-T2NODSP-NEXT: adds r2, r0, r1
; CHECK-T2NODSP-NEXT: mov.w r3, #0
; CHECK-T2NODSP-NEXT: mov.w r1, #-2147483648
; CHECK-T2NODSP-NEXT: it mi
; CHECK-T2NODSP-NEXT: movmi r3, #1
; CHECK-T2NODSP-NEXT: cmp r3, #0
; CHECK-T2NODSP-NEXT: it ne
; CHECK-T2NODSP-NEXT: mvnne r1, #-2147483648
; CHECK-T2NODSP-NEXT: cmp r2, r0
; CHECK-T2NODSP-NEXT: it vc
; CHECK-T2NODSP-NEXT: movvc r1, r2
; CHECK-T2NODSP-NEXT: mov r0, r1
; CHECK-T2NODSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
;
[ARM] Add qadd lowering from a sadd_sat This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
2019-10-21 14:33:46 +02:00
; CHECK-T2DSP-LABEL: func:
; CHECK-T2DSP: @ %bb.0:
; CHECK-T2DSP-NEXT: qadd r0, r0, r1
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARMNODPS-LABEL: func:
; CHECK-ARMNODPS: @ %bb.0:
; CHECK-ARMNODPS-NEXT: adds r2, r0, r1
; CHECK-ARMNODPS-NEXT: mov r3, #0
; CHECK-ARMNODPS-NEXT: movmi r3, #1
; CHECK-ARMNODPS-NEXT: mov r1, #-2147483648
; CHECK-ARMNODPS-NEXT: cmp r3, #0
; CHECK-ARMNODPS-NEXT: mvnne r1, #-2147483648
; CHECK-ARMNODPS-NEXT: cmp r2, r0
; CHECK-ARMNODPS-NEXT: movvc r1, r2
; CHECK-ARMNODPS-NEXT: mov r0, r1
; CHECK-ARMNODPS-NEXT: bx lr
;
; CHECK-ARMBASEDSP-LABEL: func:
; CHECK-ARMBASEDSP: @ %bb.0:
; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
; CHECK-ARMBASEDSP-NEXT: bx lr
;
; CHECK-ARMDSP-LABEL: func:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
; CHECK-ARMDSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
%tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y)
ret i32 %tmp
}
define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-LABEL: func2:
; CHECK-T1: @ %bb.0:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: .save {r4, lr}
; CHECK-T1-NEXT: push {r4, lr}
; CHECK-T1-NEXT: mov r4, r1
; CHECK-T1-NEXT: eors r4, r3
; CHECK-T1-NEXT: adds r0, r0, r2
; CHECK-T1-NEXT: adcs r3, r1
; CHECK-T1-NEXT: eors r1, r3
; CHECK-T1-NEXT: bics r1, r4
; CHECK-T1-NEXT: bpl .LBB1_2
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: @ %bb.1:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: asrs r0, r3, #31
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB1_2:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: cmp r3, #0
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-23 18:40:30 +01:00
; CHECK-T1-NEXT: bmi .LBB1_4
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: @ %bb.3:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bpl .LBB1_5
; CHECK-T1-NEXT: b .LBB1_6
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB1_4:
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: ldr r2, .LCPI1_0
; CHECK-T1-NEXT: cmp r1, #0
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-23 18:40:30 +01:00
; CHECK-T1-NEXT: bmi .LBB1_6
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: .LBB1_5:
; CHECK-T1-NEXT: mov r2, r3
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB1_6:
; CHECK-T1-NEXT: mov r1, r2
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: pop {r4, pc}
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .p2align 2
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T1-NEXT: @ %bb.7:
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LCPI1_0:
; CHECK-T1-NEXT: .long 2147483647 @ 0x7fffffff
;
; CHECK-T2-LABEL: func2:
; CHECK-T2: @ %bb.0:
; CHECK-T2-NEXT: adds r0, r0, r2
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T2-NEXT: eor.w r12, r1, r3
; CHECK-T2-NEXT: adc.w r2, r1, r3
; CHECK-T2-NEXT: eors r1, r2
; CHECK-T2-NEXT: bic.w r3, r1, r12
; CHECK-T2-NEXT: mov.w r1, #-2147483648
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. This code creates 3 setccs that need to be expanded. It was creating a sign bit test as setge X, 0 which is non-canonical. Canonical would be setgt X, -1. This misses the special case in IntegerExpandSetCCOperands for sign bit tests that assumes canonical form. If we don't hit this special case we end up with a multipart setcc instead of just checking the sign of the high part. To fix this I've reversed the polarity of all of the setccs to setlt X, 0 which is canonical. The rest of the logic should still work. This seems to produce better code on RISCV which lacks a setgt instruction. This probably still isn't the best code sequence we could use here. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97181
2021-02-23 18:40:30 +01:00
; CHECK-T2-NEXT: cmp r3, #0
; CHECK-T2-NEXT: it mi
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T2-NEXT: asrmi r0, r2, #31
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T2-NEXT: cmp r2, #0
; CHECK-T2-NEXT: it mi
; CHECK-T2-NEXT: mvnmi r1, #-2147483648
; CHECK-T2-NEXT: cmp r3, #0
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-T2-NEXT: it pl
; CHECK-T2-NEXT: movpl r1, r2
; CHECK-T2-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
;
; CHECK-ARM-LABEL: func2:
; CHECK-ARM: @ %bb.0:
[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC llvm-svn: 375401
2019-10-21 11:43:37 +02:00
; CHECK-ARM-NEXT: adds r0, r0, r2
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-ARM-NEXT: eor r12, r1, r3
; CHECK-ARM-NEXT: adc r2, r1, r3
; CHECK-ARM-NEXT: eor r1, r1, r2
; CHECK-ARM-NEXT: bic r3, r1, r12
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-ARM-NEXT: mov r1, #-2147483648
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-ARM-NEXT: cmp r3, #0
; CHECK-ARM-NEXT: asrmi r0, r2, #31
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-ARM-NEXT: cmp r2, #0
[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC llvm-svn: 375401
2019-10-21 11:43:37 +02:00
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
; CHECK-ARM-NEXT: cmp r3, #0
[LegalizeIntegerTypes] Further improve ExpandIntRes_SADDSUBO for targets where SADDO/SSUBO aren't supported. Rather than converting 3 signbits to bools and comparing them, we can do bitwise logic on the whole vector and convert the resulting sign bit to a bool at the end. This is still a different algorithm than what we do in LegalizeDAG through expandSADDOSSUBO. That algorithm needs to know that the RHS of SSUBO is > 0, but that's costly when the type is split. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D97325
2021-02-24 18:36:28 +01:00
; CHECK-ARM-NEXT: movpl r1, r2
; CHECK-ARM-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
ret i64 %tmp
}
[Codegen] Adjust saturation test. NFC. Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be. llvm-svn: 375009
2019-10-16 17:50:42 +02:00
define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-LABEL: func16:
; CHECK-T1: @ %bb.0:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: adds r0, r0, r1
; CHECK-T1-NEXT: ldr r1, .LCPI2_0
; CHECK-T1-NEXT: cmp r0, r1
; CHECK-T1-NEXT: blt .LBB2_2
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: @ %bb.1:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: mov r0, r1
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB2_2:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: ldr r1, .LCPI2_1
Revert 374373: [Codegen] Alter the default promotion for saturating adds and subs This commit is not extending the promoted integers as it should. Reverting whilst I look into the details. llvm-svn: 374592
2019-10-11 22:33:03 +02:00
; CHECK-T1-NEXT: cmp r0, r1
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: bgt .LBB2_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r0, r1
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB2_4:
; CHECK-T1-NEXT: bx lr
; CHECK-T1-NEXT: .p2align 2
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: @ %bb.5:
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LCPI2_0:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: .long 32767 @ 0x7fff
; CHECK-T1-NEXT: .LCPI2_1:
; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
;
[ARM] Lower sadd_sat to qadd8 and qadd16 Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
2019-10-21 11:53:38 +02:00
; CHECK-T2NODSP-LABEL: func16:
; CHECK-T2NODSP: @ %bb.0:
; CHECK-T2NODSP-NEXT: add r0, r1
; CHECK-T2NODSP-NEXT: movw r1, #32767
; CHECK-T2NODSP-NEXT: cmp r0, r1
; CHECK-T2NODSP-NEXT: it lt
; CHECK-T2NODSP-NEXT: movlt r1, r0
; CHECK-T2NODSP-NEXT: movw r0, #32768
; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
; CHECK-T2NODSP-NEXT: movt r0, #65535
; CHECK-T2NODSP-NEXT: it gt
; CHECK-T2NODSP-NEXT: movgt r0, r1
; CHECK-T2NODSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
;
[ARM] Lower sadd_sat to qadd8 and qadd16 Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
2019-10-21 11:53:38 +02:00
; CHECK-T2DSP-LABEL: func16:
; CHECK-T2DSP: @ %bb.0:
; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
; CHECK-T2DSP-NEXT: sxth r0, r0
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARMNODPS-LABEL: func16:
; CHECK-ARMNODPS: @ %bb.0:
; CHECK-ARMNODPS-NEXT: add r0, r0, r1
; CHECK-ARMNODPS-NEXT: mov r1, #255
; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
; CHECK-ARMNODPS-NEXT: cmp r0, r1
; CHECK-ARMNODPS-NEXT: movlt r1, r0
; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
; CHECK-ARMNODPS-NEXT: cmn r1, #32768
; CHECK-ARMNODPS-NEXT: movgt r0, r1
; CHECK-ARMNODPS-NEXT: bx lr
; CHECK-ARMNODPS-NEXT: .p2align 2
; CHECK-ARMNODPS-NEXT: @ %bb.1:
; CHECK-ARMNODPS-NEXT: .LCPI2_0:
; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
;
; CHECK-ARMBASEDSP-LABEL: func16:
; CHECK-ARMBASEDSP: @ %bb.0:
[ARM] Add qadd lowering from a sadd_sat This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
2019-10-21 14:33:46 +02:00
; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #16
; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #16
; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #16
[ARM] Lower sadd_sat to qadd8 and qadd16 Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
2019-10-21 11:53:38 +02:00
; CHECK-ARMBASEDSP-NEXT: bx lr
;
; CHECK-ARMDSP-LABEL: func16:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: qadd16 r0, r0, r1
; CHECK-ARMDSP-NEXT: sxth r0, r0
; CHECK-ARMDSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
ret i16 %tmp
}
[Codegen] Adjust saturation test. NFC. Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be. llvm-svn: 375009
2019-10-16 17:50:42 +02:00
define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-LABEL: func8:
; CHECK-T1: @ %bb.0:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: adds r0, r0, r1
; CHECK-T1-NEXT: movs r1, #127
; CHECK-T1-NEXT: cmp r0, #127
; CHECK-T1-NEXT: blt .LBB3_2
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: @ %bb.1:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: mov r0, r1
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB3_2:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: mvns r1, r1
Revert 374373: [Codegen] Alter the default promotion for saturating adds and subs This commit is not extending the promoted integers as it should. Reverting whilst I look into the details. llvm-svn: 374592
2019-10-11 22:33:03 +02:00
; CHECK-T1-NEXT: cmp r0, r1
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: bgt .LBB3_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r0, r1
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB3_4:
; CHECK-T1-NEXT: bx lr
;
[ARM] Lower sadd_sat to qadd8 and qadd16 Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
2019-10-21 11:53:38 +02:00
; CHECK-T2NODSP-LABEL: func8:
; CHECK-T2NODSP: @ %bb.0:
; CHECK-T2NODSP-NEXT: add r0, r1
; CHECK-T2NODSP-NEXT: cmp r0, #127
; CHECK-T2NODSP-NEXT: it ge
; CHECK-T2NODSP-NEXT: movge r0, #127
; CHECK-T2NODSP-NEXT: cmn.w r0, #128
; CHECK-T2NODSP-NEXT: it le
; CHECK-T2NODSP-NEXT: mvnle r0, #127
; CHECK-T2NODSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
;
[ARM] Lower sadd_sat to qadd8 and qadd16 Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
2019-10-21 11:53:38 +02:00
; CHECK-T2DSP-LABEL: func8:
; CHECK-T2DSP: @ %bb.0:
; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
; CHECK-T2DSP-NEXT: sxtb r0, r0
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARMNODPS-LABEL: func8:
; CHECK-ARMNODPS: @ %bb.0:
; CHECK-ARMNODPS-NEXT: add r0, r0, r1
; CHECK-ARMNODPS-NEXT: cmp r0, #127
; CHECK-ARMNODPS-NEXT: movge r0, #127
; CHECK-ARMNODPS-NEXT: cmn r0, #128
; CHECK-ARMNODPS-NEXT: mvnle r0, #127
; CHECK-ARMNODPS-NEXT: bx lr
;
; CHECK-ARMBASEDSP-LABEL: func8:
; CHECK-ARMBASEDSP: @ %bb.0:
[ARM] Add qadd lowering from a sadd_sat This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
2019-10-21 14:33:46 +02:00
; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #24
; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #24
; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #24
[ARM] Lower sadd_sat to qadd8 and qadd16 Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
2019-10-21 11:53:38 +02:00
; CHECK-ARMBASEDSP-NEXT: bx lr
;
; CHECK-ARMDSP-LABEL: func8:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: qadd8 r0, r0, r1
; CHECK-ARMDSP-NEXT: sxtb r0, r0
; CHECK-ARMDSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
ret i8 %tmp
}
[Codegen] Adjust saturation test. NFC. Add some extra sat tests and adjust some of the existing tests to use signext where it would naturally be. llvm-svn: 375009
2019-10-16 17:50:42 +02:00
define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-LABEL: func3:
; CHECK-T1: @ %bb.0:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: adds r0, r0, r1
; CHECK-T1-NEXT: movs r1, #7
; CHECK-T1-NEXT: cmp r0, #7
; CHECK-T1-NEXT: blt .LBB4_2
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: @ %bb.1:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: mov r0, r1
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB4_2:
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: mvns r1, r1
Revert 374373: [Codegen] Alter the default promotion for saturating adds and subs This commit is not extending the promoted integers as it should. Reverting whilst I look into the details. llvm-svn: 374592
2019-10-11 22:33:03 +02:00
; CHECK-T1-NEXT: cmp r0, r1
[Codegen] Alter the default promotion for saturating adds and subs The default promotion for the add_sat/sub_sat nodes currently does: ANY_EXTEND iN to iM SHL by M-N [US][ADD|SUB]SAT L/ASHR by M-N If the promoted add_sat or sub_sat node is not legal, this can produce code that effectively does a lot of shifting (and requiring large constants to be materialised) just to use the overflow flag. It is simpler to just do the saturation manually, using the higher bitwidth addition and a min/max against the saturating bounds. That is what this patch attempts to do. Differential Revision: https://reviews.llvm.org/D68926 llvm-svn: 375211
2019-10-18 11:47:48 +02:00
; CHECK-T1-NEXT: bgt .LBB4_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r0, r1
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
; CHECK-T1-NEXT: .LBB4_4:
; CHECK-T1-NEXT: bx lr
;
[ARM] Add qadd lowering from a sadd_sat This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
2019-10-21 14:33:46 +02:00
; CHECK-T2NODSP-LABEL: func3:
; CHECK-T2NODSP: @ %bb.0:
; CHECK-T2NODSP-NEXT: add r0, r1
; CHECK-T2NODSP-NEXT: cmp r0, #7
; CHECK-T2NODSP-NEXT: it ge
; CHECK-T2NODSP-NEXT: movge r0, #7
; CHECK-T2NODSP-NEXT: cmn.w r0, #8
; CHECK-T2NODSP-NEXT: it le
; CHECK-T2NODSP-NEXT: mvnle r0, #7
; CHECK-T2NODSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
;
[ARM] Add qadd lowering from a sadd_sat This lowers a sadd_sat to a qadd by treating it as legal. Also adds qsub at the same time. The qadd instruction sets the q flag, but we already have many cases where we do not model this in llvm. Differential Revision: https://reviews.llvm.org/D68976 llvm-svn: 375411
2019-10-21 14:33:46 +02:00
; CHECK-T2DSP-LABEL: func3:
; CHECK-T2DSP: @ %bb.0:
; CHECK-T2DSP-NEXT: lsls r1, r1, #28
; CHECK-T2DSP-NEXT: lsls r0, r0, #28
; CHECK-T2DSP-NEXT: qadd r0, r0, r1
; CHECK-T2DSP-NEXT: asrs r0, r0, #28
; CHECK-T2DSP-NEXT: bx lr
;
; CHECK-ARMNODPS-LABEL: func3:
; CHECK-ARMNODPS: @ %bb.0:
; CHECK-ARMNODPS-NEXT: add r0, r0, r1
; CHECK-ARMNODPS-NEXT: cmp r0, #7
; CHECK-ARMNODPS-NEXT: movge r0, #7
; CHECK-ARMNODPS-NEXT: cmn r0, #8
; CHECK-ARMNODPS-NEXT: mvnle r0, #7
; CHECK-ARMNODPS-NEXT: bx lr
;
; CHECK-ARMBASEDSP-LABEL: func3:
; CHECK-ARMBASEDSP: @ %bb.0:
; CHECK-ARMBASEDSP-NEXT: lsl r0, r0, #28
; CHECK-ARMBASEDSP-NEXT: lsl r1, r1, #28
; CHECK-ARMBASEDSP-NEXT: qadd r0, r0, r1
; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #28
; CHECK-ARMBASEDSP-NEXT: bx lr
;
; CHECK-ARMDSP-LABEL: func3:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: lsl r0, r0, #28
; CHECK-ARMDSP-NEXT: lsl r1, r1, #28
; CHECK-ARMDSP-NEXT: qadd r0, r0, r1
; CHECK-ARMDSP-NEXT: asr r0, r0, #28
; CHECK-ARMDSP-NEXT: bx lr
Add and adjust saturating tests. NFC This adds some extra testing to the existing [su][add/sub]_sat X86 and AArch64 tests and adds equivalent tests for ARM. llvm-svn: 374169
2019-10-09 16:17:38 +02:00
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y)
ret i4 %tmp
}
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