llvm-mirror/test/CodeGen/PowerPC/ppcf128-4.ll

; RUN: llc < %s -march=ppc32

define ppc_fp128 @__floatditf(i64 %u) nounwind  {
entry:
        %tmp6 = fmul ppc_fp128 0xM00000000000000000000000000000000, 0xM41F00000000000000000000000000000
        %tmp78 = trunc i64 %u to i32
        %tmp789 = uitofp i32 %tmp78 to ppc_fp128
        %tmp11 = fadd ppc_fp128 %tmp789, %tmp6
        ret ppc_fp128 %tmp11
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293 2009-09-09 02:09:15 +02:00			`; RUN: llc < %s -march=ppc32`
New testcase. llvm-svn: 48697 2008-03-22 23:27:01 +01:00
			`define ppc_fp128 @__floatditf(i64 %u) nounwind {`
			`entry:`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 00:49:04 +02:00			`%tmp6 = fmul ppc_fp128 0xM00000000000000000000000000000000, 0xM41F00000000000000000000000000000`
New testcase. llvm-svn: 48697 2008-03-22 23:27:01 +01:00			`%tmp78 = trunc i64 %u to i32`
			`%tmp789 = uitofp i32 %tmp78 to ppc_fp128`
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897 2009-06-05 00:49:04 +02:00			`%tmp11 = fadd ppc_fp128 %tmp789, %tmp6`
New testcase. llvm-svn: 48697 2008-03-22 23:27:01 +01:00			`ret ppc_fp128 %tmp11`
			`}`