llvm-mirror/lib/Target/R600/SIDefines.h

//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
/// \file
//===----------------------------------------------------------------------===//

#ifndef SIDEFINES_H_
#define SIDEFINES_H_

namespace SIInstrFlags {
enum {
  MIMG = 1 << 3,
  SMRD = 1 << 4
};
}

#define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS                                0x00B02C
#define   S_00B02C_EXTRA_LDS_SIZE(x)                                  (((x) & 0xFF) << 8)
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS                                0x00B128
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS                                0x00B228
#define R_00B848_COMPUTE_PGM_RSRC1                                      0x00B848
#define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
#define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
#define R_00B84C_COMPUTE_PGM_RSRC2                                      0x00B84C
#define   S_00B84C_LDS_SIZE(x)                                        (((x) & 0x1FF) << 15)
#define R_0286CC_SPI_PS_INPUT_ENA                                       0x0286CC

#endif // SIDEFINES_H_
R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546 2013-04-15 19:51:35 +02:00			`//===-- SIDefines.h - SI Helper Macros ----------------------- C++ --===//`
			`//`
			`// The LLVM Compiler Infrastructure`
			`//`
			`// This file is distributed under the University of Illinois Open Source`
			`// License. See LICENSE.TXT for details.`
			`//`
			`/// \file`
			`//===----------------------------------------------------------------------===//`

			`#ifndef SIDEFINES_H_`
			`#define SIDEFINES_H_`

R600/SI: Assign a register class to the $vaddr operand for MIMG instructions The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425 2013-08-15 01:24:17 +02:00			`namespace SIInstrFlags {`
			`enum {`
R600/SI: Fix broken encoding of DS_WRITE_B32 The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188558 2013-08-16 18:19:24 +02:00			`MIMG = 1 << 3,`
			`SMRD = 1 << 4`
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425 2013-08-15 01:24:17 +02:00			`};`
			`}`

R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546 2013-04-15 19:51:35 +02:00			`#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028`
R600/SI: Initial local memory support Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012 2013-07-10 18:37:07 +02:00			`#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C`
			`#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)`
R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546 2013-04-15 19:51:35 +02:00			`#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128`
			`#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228`
			`#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848`
			`#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)`
			`#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)`
R600/SI: Initial local memory support Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012 2013-07-10 18:37:07 +02:00			`#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C`
			`#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)`
R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546 2013-04-15 19:51:35 +02:00			`#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC`

			`#endif // SIDEFINES_H_`