2003-09-30 20:37:50 +02:00
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//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
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2005-04-21 22:39:54 +02:00
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//
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2003-10-20 22:19:47 +02:00
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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2005-04-21 22:39:54 +02:00
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//
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2003-10-20 22:19:47 +02:00
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//===----------------------------------------------------------------------===//
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2002-02-03 08:11:59 +01:00
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//
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// This file contains the declaration of the MachineInstr class, which is the
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2003-08-22 00:14:26 +02:00
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// basic representation for all target dependent machine instructions used by
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2002-02-03 08:11:59 +01:00
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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2001-07-21 14:39:03 +02:00
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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2004-09-02 00:55:40 +02:00
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#include "llvm/ADT/iterator"
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2005-04-10 11:18:55 +02:00
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/Streams.h"
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2004-02-10 22:21:17 +01:00
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#include <vector>
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2004-02-29 06:15:56 +01:00
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#include <cassert>
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2006-11-18 22:47:36 +01:00
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#include <iosfwd>
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2003-06-11 16:01:36 +02:00
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2003-11-11 23:41:34 +01:00
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namespace llvm {
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2002-10-28 03:29:46 +01:00
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class Value;
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class Function;
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2002-10-30 00:18:23 +01:00
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class MachineBasicBlock;
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2006-11-14 00:34:06 +01:00
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class TargetInstrDescriptor;
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class TargetMachine;
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class GlobalValue;
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2002-10-28 03:29:46 +01:00
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2004-10-27 18:14:51 +02:00
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template <typename T> struct ilist_traits;
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template <typename T> struct ilist;
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2004-02-12 03:27:10 +01:00
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2003-06-03 17:42:53 +02:00
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//===----------------------------------------------------------------------===//
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2005-04-21 22:39:54 +02:00
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// class MachineOperand
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//
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2001-07-21 14:39:03 +02:00
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// Representation of each machine instruction operand.
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2005-04-22 05:46:24 +02:00
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//
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2003-01-13 01:18:17 +01:00
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struct MachineOperand {
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enum MachineOperandType {
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MO_Register, // Register operand.
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MO_Immediate, // Immediate Operand
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MO_MachineBasicBlock, // MachineBasicBlock reference
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MO_FrameIndex, // Abstract Stack Frame Index
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MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
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MO_JumpTableIndex, // Address of indexed Jump Table for switch
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MO_ExternalSymbol, // Name of external global symbol
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MO_GlobalAddress // Address of a global value
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2001-07-21 14:39:03 +02:00
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};
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2001-07-28 06:06:37 +02:00
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private:
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union {
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2006-05-04 21:36:09 +02:00
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GlobalValue *GV; // For MO_GlobalAddress.
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
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const char *SymbolName; // For MO_ExternalSymbol.
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unsigned RegNo; // For MO_Register.
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int64_t immedVal; // For MO_Immediate and MO_*Index.
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2004-03-03 20:07:27 +01:00
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} contents;
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2001-08-07 22:14:30 +02:00
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2006-09-05 04:31:13 +02:00
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MachineOperandType opType:8; // Discriminate the union.
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bool IsDef : 1; // True if this is a def, false if this is a use.
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bool IsImp : 1; // True if this is an implicit def or use.
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2006-11-14 00:34:06 +01:00
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bool IsKill : 1; // True if this is a reg use and the reg is dead
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// immediately after the read.
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bool IsDead : 1; // True if this is a reg def and the reg is dead
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// immediately after the write. i.e. A register
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// that is defined but never used.
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2006-05-04 20:25:20 +02:00
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2007-05-01 07:57:02 +02:00
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/// auxInfo - auxiliary information used by the MachineOperand
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union {
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/// offset - Offset to address of global or external, only valid for
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/// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
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int offset;
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2007-11-14 08:59:08 +01:00
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/// subReg - SubRegister number, only valid for MO_Register. A value of 0
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/// indicates the MO_Register has no subReg.
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2007-11-17 01:31:16 +01:00
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unsigned char subReg;
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2007-05-01 07:57:02 +02:00
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} auxInfo;
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2006-05-04 21:14:44 +02:00
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MachineOperand() {}
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2006-12-16 03:15:42 +01:00
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void print(std::ostream &os) const;
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2006-12-17 06:15:13 +01:00
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void print(std::ostream *os) const { if (os) print(*os); }
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2006-12-16 03:15:42 +01:00
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2001-07-28 06:06:37 +02:00
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public:
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2006-05-04 20:25:20 +02:00
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MachineOperand(const MachineOperand &M) {
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*this = M;
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2003-01-13 01:18:17 +01:00
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}
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2006-10-20 20:00:03 +02:00
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2004-11-19 21:46:15 +01:00
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~MachineOperand() {}
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2006-10-20 20:00:03 +02:00
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static MachineOperand CreateImm(int64_t Val) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Immediate;
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Op.contents.immedVal = Val;
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Op.IsDef = false;
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2006-11-10 09:32:14 +01:00
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Op.IsImp = false;
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2006-11-14 00:34:06 +01:00
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Op.IsKill = false;
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Op.IsDead = false;
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2007-05-01 07:57:02 +02:00
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Op.auxInfo.offset = 0;
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2006-10-20 20:00:03 +02:00
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return Op;
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}
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2007-08-30 07:50:32 +02:00
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static MachineOperand CreateFrameIndex(unsigned Idx) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_FrameIndex;
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Op.contents.immedVal = Idx;
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Op.IsDef = false;
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Op.IsImp = false;
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Op.IsKill = false;
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Op.IsDead = false;
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Op.auxInfo.offset = 0;
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return Op;
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}
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2003-01-13 01:18:17 +01:00
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const MachineOperand &operator=(const MachineOperand &MO) {
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contents = MO.contents;
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2006-09-05 04:31:13 +02:00
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IsDef = MO.IsDef;
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2006-11-10 09:32:14 +01:00
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IsImp = MO.IsImp;
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2006-11-14 00:34:06 +01:00
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IsKill = MO.IsKill;
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IsDead = MO.IsDead;
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2003-01-13 01:18:17 +01:00
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opType = MO.opType;
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2007-05-01 07:57:02 +02:00
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auxInfo = MO.auxInfo;
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2003-01-13 01:18:17 +01:00
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return *this;
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}
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2004-02-12 05:26:49 +01:00
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/// getType - Returns the MachineOperandType for this operand.
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2005-04-21 22:39:54 +02:00
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///
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2002-10-28 05:45:29 +01:00
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MachineOperandType getType() const { return opType; }
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2002-10-28 05:24:49 +01:00
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2004-03-03 20:07:27 +01:00
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/// Accessors that tell you what kind of MachineOperand you're looking at.
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///
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2006-05-04 20:05:43 +02:00
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bool isRegister() const { return opType == MO_Register; }
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2006-05-04 19:21:20 +02:00
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bool isImmediate() const { return opType == MO_Immediate; }
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2006-05-04 19:56:20 +02:00
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bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
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2002-12-25 06:00:49 +01:00
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bool isFrameIndex() const { return opType == MO_FrameIndex; }
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2003-01-13 01:18:17 +01:00
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bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
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2006-04-22 20:53:45 +02:00
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bool isJumpTableIndex() const { return opType == MO_JumpTableIndex; }
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2003-01-13 01:18:17 +01:00
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bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
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bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
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2002-11-22 23:40:52 +01:00
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2006-09-05 01:35:22 +02:00
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int64_t getImm() const {
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2007-09-14 22:33:02 +02:00
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assert(isImmediate() && "Wrong MachineOperand accessor");
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2006-09-05 01:35:22 +02:00
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return contents.immedVal;
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}
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2005-04-10 11:18:55 +02:00
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int64_t getImmedValue() const {
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2007-09-14 22:33:02 +02:00
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assert(isImmediate() && "Wrong MachineOperand accessor");
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2004-03-03 20:07:27 +01:00
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return contents.immedVal;
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}
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2006-10-21 00:39:36 +02:00
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MachineBasicBlock *getMBB() const {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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2002-12-15 09:01:02 +01:00
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MachineBasicBlock *getMachineBasicBlock() const {
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2004-03-03 20:07:27 +01:00
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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return contents.MBB;
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}
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2004-07-31 03:59:11 +02:00
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void setMachineBasicBlock(MachineBasicBlock *MBB) {
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assert(isMachineBasicBlock() && "Wrong MachineOperand accessor");
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contents.MBB = MBB;
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}
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2004-03-03 20:07:27 +01:00
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int getFrameIndex() const {
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assert(isFrameIndex() && "Wrong MachineOperand accessor");
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2005-04-11 05:38:28 +02:00
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return (int)contents.immedVal;
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2002-12-15 09:01:02 +01:00
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}
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2003-01-13 01:18:17 +01:00
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unsigned getConstantPoolIndex() const {
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2004-03-03 20:07:27 +01:00
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assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
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2005-04-11 05:38:28 +02:00
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return (unsigned)contents.immedVal;
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2003-01-13 01:18:17 +01:00
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}
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2006-04-22 20:53:45 +02:00
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unsigned getJumpTableIndex() const {
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assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
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return (unsigned)contents.immedVal;
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}
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2003-01-13 01:18:17 +01:00
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GlobalValue *getGlobal() const {
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2004-03-03 20:07:27 +01:00
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assert(isGlobalAddress() && "Wrong MachineOperand accessor");
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2006-05-04 19:02:51 +02:00
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return contents.GV;
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2003-01-13 01:18:17 +01:00
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}
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2004-10-15 06:38:41 +02:00
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int getOffset() const {
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2006-02-25 10:54:52 +01:00
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assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
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2004-10-15 06:38:41 +02:00
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"Wrong MachineOperand accessor");
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2007-05-01 07:57:02 +02:00
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return auxInfo.offset;
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}
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2007-11-14 08:59:08 +01:00
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unsigned getSubReg() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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2007-11-17 01:31:16 +01:00
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return (unsigned)auxInfo.subReg;
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2007-11-14 08:59:08 +01:00
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}
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2004-11-19 21:46:15 +01:00
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const char *getSymbolName() const {
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2004-03-03 20:07:27 +01:00
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assert(isExternalSymbol() && "Wrong MachineOperand accessor");
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2004-11-19 21:46:15 +01:00
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return contents.SymbolName;
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2003-01-13 01:18:17 +01:00
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}
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2002-12-15 09:01:02 +01:00
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2006-09-05 22:20:04 +02:00
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bool isUse() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return !IsDef;
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}
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bool isDef() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsDef;
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}
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void setIsUse() {
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsDef = false;
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}
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void setIsDef() {
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsDef = true;
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}
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2002-09-16 17:58:54 +02:00
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2006-11-10 09:32:14 +01:00
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bool isImplicit() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsImp;
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}
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2006-11-10 15:44:12 +01:00
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void setImplicit() {
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2006-11-10 09:32:14 +01:00
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assert(isRegister() && "Wrong MachineOperand accessor");
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IsImp = true;
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}
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2006-11-14 00:34:06 +01:00
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bool isKill() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsKill;
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}
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bool isDead() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsDead;
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}
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void setIsKill() {
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2006-11-15 21:48:17 +01:00
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assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
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2006-11-14 00:34:06 +01:00
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IsKill = true;
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}
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void setIsDead() {
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2006-11-15 21:48:17 +01:00
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assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
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2006-11-14 00:34:06 +01:00
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IsDead = true;
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}
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void unsetIsKill() {
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2006-11-15 21:48:17 +01:00
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assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
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2006-11-14 00:34:06 +01:00
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IsKill = false;
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}
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void unsetIsDead() {
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2006-11-15 21:48:17 +01:00
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assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
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2006-11-14 00:34:06 +01:00
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IsDead = false;
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}
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2006-05-04 19:56:20 +02:00
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/// getReg - Returns the register number.
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2004-03-03 20:07:27 +01:00
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///
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2004-02-13 22:01:20 +01:00
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unsigned getReg() const {
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2006-05-04 19:56:20 +02:00
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assert(isRegister() && "This is not a register operand!");
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2006-05-04 20:25:20 +02:00
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return contents.RegNo;
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2002-07-09 00:38:45 +02:00
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}
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2002-09-16 17:58:54 +02:00
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2006-05-04 03:26:39 +02:00
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/// MachineOperand mutators.
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2004-03-03 20:07:27 +01:00
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///
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2003-12-01 06:30:29 +01:00
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void setReg(unsigned Reg) {
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2006-05-04 19:56:20 +02:00
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assert(isRegister() && "This is not a register operand!");
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2006-05-04 20:25:20 +02:00
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contents.RegNo = Reg;
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2005-04-21 22:39:54 +02:00
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}
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2004-06-25 02:13:11 +02:00
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2006-05-04 19:52:23 +02:00
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void setImmedValue(int64_t immVal) {
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2007-09-14 22:33:02 +02:00
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assert(isImmediate() && "Wrong MachineOperand mutator");
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2006-09-05 01:35:22 +02:00
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contents.immedVal = immVal;
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}
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void setImm(int64_t immVal) {
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2007-09-14 22:33:02 +02:00
|
|
|
assert(isImmediate() && "Wrong MachineOperand mutator");
|
2004-03-03 20:07:27 +01:00
|
|
|
contents.immedVal = immVal;
|
|
|
|
}
|
2003-05-31 09:43:01 +02:00
|
|
|
|
2004-10-15 06:38:41 +02:00
|
|
|
void setOffset(int Offset) {
|
2006-04-22 20:53:45 +02:00
|
|
|
assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
|
|
|
|
isJumpTableIndex()) &&
|
2004-10-15 06:38:41 +02:00
|
|
|
"Wrong MachineOperand accessor");
|
2007-05-01 07:57:02 +02:00
|
|
|
auxInfo.offset = Offset;
|
|
|
|
}
|
2007-11-14 08:59:08 +01:00
|
|
|
void setSubReg(unsigned subReg) {
|
|
|
|
assert(isRegister() && "Wrong MachineOperand accessor");
|
2007-11-17 01:31:16 +01:00
|
|
|
auxInfo.subReg = (unsigned char)subReg;
|
2007-11-14 08:59:08 +01:00
|
|
|
}
|
2006-10-06 03:16:29 +02:00
|
|
|
void setConstantPoolIndex(unsigned Idx) {
|
|
|
|
assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
|
|
|
|
contents.immedVal = Idx;
|
|
|
|
}
|
2006-10-28 20:18:36 +02:00
|
|
|
void setJumpTableIndex(unsigned Idx) {
|
|
|
|
assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
|
|
|
|
contents.immedVal = Idx;
|
|
|
|
}
|
2006-10-06 03:16:29 +02:00
|
|
|
|
2006-10-21 00:39:36 +02:00
|
|
|
/// isIdenticalTo - Return true if this operand is identical to the specified
|
2006-11-15 21:48:17 +01:00
|
|
|
/// operand. Note: This method ignores isKill and isDead properties.
|
2006-10-21 00:39:36 +02:00
|
|
|
bool isIdenticalTo(const MachineOperand &Other) const;
|
2006-05-04 19:52:23 +02:00
|
|
|
|
|
|
|
/// ChangeToImmediate - Replace this operand with a new immediate operand of
|
|
|
|
/// the specified value. If an operand is known to be an immediate already,
|
|
|
|
/// the setImmedValue method should be used.
|
|
|
|
void ChangeToImmediate(int64_t ImmVal) {
|
|
|
|
opType = MO_Immediate;
|
|
|
|
contents.immedVal = ImmVal;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// ChangeToRegister - Replace this operand with a new register operand of
|
|
|
|
/// the specified value. If an operand is known to be an register already,
|
|
|
|
/// the setReg method should be used.
|
2007-02-27 22:06:57 +01:00
|
|
|
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
|
|
|
|
bool isKill = false, bool isDead = false) {
|
2006-05-04 20:05:43 +02:00
|
|
|
opType = MO_Register;
|
2006-05-04 20:25:20 +02:00
|
|
|
contents.RegNo = Reg;
|
2006-09-05 04:31:13 +02:00
|
|
|
IsDef = isDef;
|
2007-02-27 22:06:57 +01:00
|
|
|
IsImp = isImp;
|
|
|
|
IsKill = isKill;
|
|
|
|
IsDead = isDead;
|
2006-05-04 19:52:23 +02:00
|
|
|
}
|
2004-10-15 06:38:41 +02:00
|
|
|
|
2006-12-16 03:15:42 +01:00
|
|
|
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
|
|
|
|
mop.print(os);
|
|
|
|
return os;
|
|
|
|
}
|
2001-08-09 21:18:33 +02:00
|
|
|
|
2002-07-10 23:50:57 +02:00
|
|
|
friend class MachineInstr;
|
2001-07-21 14:39:03 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
2003-06-03 17:42:53 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2006-05-04 20:16:01 +02:00
|
|
|
/// MachineInstr - Representation of each machine instruction.
|
|
|
|
///
|
2003-06-03 00:07:37 +02:00
|
|
|
class MachineInstr {
|
2006-11-30 08:08:44 +01:00
|
|
|
const TargetInstrDescriptor *TID; // Instruction descriptor.
|
2006-11-28 00:37:22 +01:00
|
|
|
unsigned short NumImplicitOps; // Number of implicit operands (which
|
2006-11-15 21:48:17 +01:00
|
|
|
// are determined at construction time).
|
|
|
|
|
2006-05-04 21:14:44 +02:00
|
|
|
std::vector<MachineOperand> Operands; // the operands
|
2004-02-12 03:27:10 +01:00
|
|
|
MachineInstr* prev, *next; // links for our intrusive list
|
2004-02-12 19:49:07 +01:00
|
|
|
MachineBasicBlock* parent; // pointer to the owning basic block
|
2004-03-03 20:07:27 +01:00
|
|
|
|
2002-10-28 21:48:39 +01:00
|
|
|
// OperandComplete - Return true if it's illegal to add a new operand
|
|
|
|
bool OperandsComplete() const;
|
2002-10-29 20:41:18 +01:00
|
|
|
|
2004-05-23 21:35:12 +02:00
|
|
|
MachineInstr(const MachineInstr&);
|
2003-06-03 00:07:37 +02:00
|
|
|
void operator=(const MachineInstr&); // DO NOT IMPLEMENT
|
2004-02-12 03:27:10 +01:00
|
|
|
|
|
|
|
// Intrusive list support
|
|
|
|
//
|
2004-10-27 18:14:51 +02:00
|
|
|
friend struct ilist_traits<MachineInstr>;
|
2004-02-12 03:27:10 +01:00
|
|
|
|
2001-07-21 14:39:03 +02:00
|
|
|
public:
|
2006-11-28 00:37:22 +01:00
|
|
|
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
|
2006-11-30 08:08:44 +01:00
|
|
|
/// TID NULL and no operands.
|
2006-11-28 00:37:22 +01:00
|
|
|
MachineInstr();
|
2002-09-20 02:47:49 +02:00
|
|
|
|
2006-11-14 00:34:06 +01:00
|
|
|
/// MachineInstr ctor - This constructor create a MachineInstr and add the
|
2006-11-28 00:37:22 +01:00
|
|
|
/// implicit operands. It reserves space for number of operands specified by
|
|
|
|
/// TargetInstrDescriptor.
|
2007-10-13 04:23:01 +02:00
|
|
|
explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
|
2006-11-14 00:34:06 +01:00
|
|
|
|
2002-10-30 00:18:23 +01:00
|
|
|
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
|
|
|
|
/// the MachineInstr is created and added to the end of the specified basic
|
|
|
|
/// block.
|
|
|
|
///
|
2006-11-28 00:37:22 +01:00
|
|
|
MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
|
2005-04-21 22:39:54 +02:00
|
|
|
|
2004-02-16 08:17:43 +01:00
|
|
|
~MachineInstr();
|
|
|
|
|
2004-02-12 19:49:07 +01:00
|
|
|
const MachineBasicBlock* getParent() const { return parent; }
|
|
|
|
MachineBasicBlock* getParent() { return parent; }
|
2006-11-30 08:08:44 +01:00
|
|
|
|
|
|
|
/// getInstrDescriptor - Returns the target instruction descriptor of this
|
|
|
|
/// MachineInstr.
|
|
|
|
const TargetInstrDescriptor *getInstrDescriptor() const { return TID; }
|
2004-02-12 19:49:07 +01:00
|
|
|
|
2004-03-03 20:07:27 +01:00
|
|
|
/// getOpcode - Returns the opcode of this MachineInstr.
|
2004-02-12 02:34:03 +01:00
|
|
|
///
|
2007-09-14 22:08:19 +02:00
|
|
|
int getOpcode() const;
|
2003-05-31 09:43:01 +02:00
|
|
|
|
2004-02-12 02:34:03 +01:00
|
|
|
/// Access to explicit operands of the instruction.
|
|
|
|
///
|
2006-05-04 21:14:44 +02:00
|
|
|
unsigned getNumOperands() const { return Operands.size(); }
|
2005-04-21 22:39:54 +02:00
|
|
|
|
2002-10-28 05:24:49 +01:00
|
|
|
const MachineOperand& getOperand(unsigned i) const {
|
2002-10-29 20:41:18 +01:00
|
|
|
assert(i < getNumOperands() && "getOperand() out of range!");
|
2006-05-04 21:14:44 +02:00
|
|
|
return Operands[i];
|
2002-10-28 05:24:49 +01:00
|
|
|
}
|
|
|
|
MachineOperand& getOperand(unsigned i) {
|
2002-10-29 20:41:18 +01:00
|
|
|
assert(i < getNumOperands() && "getOperand() out of range!");
|
2006-05-04 21:14:44 +02:00
|
|
|
return Operands[i];
|
2002-10-28 05:24:49 +01:00
|
|
|
}
|
2002-10-28 05:30:20 +01:00
|
|
|
|
2007-05-15 03:26:09 +02:00
|
|
|
/// getNumExplicitOperands - Returns the number of non-implicit operands.
|
|
|
|
///
|
|
|
|
unsigned getNumExplicitOperands() const;
|
2006-10-21 00:39:36 +02:00
|
|
|
|
|
|
|
/// isIdenticalTo - Return true if this instruction is identical to (same
|
|
|
|
/// opcode and same operands as) the specified instruction.
|
|
|
|
bool isIdenticalTo(const MachineInstr *Other) const {
|
|
|
|
if (Other->getOpcode() != getOpcode() ||
|
2006-10-21 00:44:45 +02:00
|
|
|
Other->getNumOperands() != getNumOperands())
|
2006-10-21 00:39:36 +02:00
|
|
|
return false;
|
|
|
|
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
|
|
|
|
if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
2002-10-29 20:41:18 +01:00
|
|
|
|
2004-05-23 22:58:02 +02:00
|
|
|
/// clone - Create a copy of 'this' instruction that is identical in
|
|
|
|
/// all ways except the the instruction has no parent, prev, or next.
|
2006-05-04 21:14:44 +02:00
|
|
|
MachineInstr* clone() const { return new MachineInstr(*this); }
|
2006-04-17 23:35:08 +02:00
|
|
|
|
|
|
|
/// removeFromParent - This method unlinks 'this' from the containing basic
|
|
|
|
/// block, and returns it, but does not delete it.
|
|
|
|
MachineInstr *removeFromParent();
|
|
|
|
|
|
|
|
/// eraseFromParent - This method unlinks 'this' from the containing basic
|
|
|
|
/// block and deletes it.
|
|
|
|
void eraseFromParent() {
|
|
|
|
delete removeFromParent();
|
|
|
|
}
|
2004-05-23 21:35:12 +02:00
|
|
|
|
2007-04-26 21:00:32 +02:00
|
|
|
/// findRegisterUseOperandIdx() - Returns the operand index that is a use of
|
2007-03-27 00:37:45 +02:00
|
|
|
/// the specific register or -1 if it is not found. It further tightening
|
2007-02-23 02:04:26 +01:00
|
|
|
/// the search criteria to a use that kills the register if isKill is true.
|
2007-05-29 20:35:22 +02:00
|
|
|
int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const;
|
2006-12-06 09:27:42 +01:00
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
|
|
|
|
/// the specific register or NULL if it is not found.
|
|
|
|
MachineOperand *findRegisterDefOperand(unsigned Reg);
|
2007-05-15 03:26:09 +02:00
|
|
|
|
2007-05-29 20:35:22 +02:00
|
|
|
/// findFirstPredOperandIdx() - Find the index of the first operand in the
|
|
|
|
/// operand list that is used to represent the predicate. It returns -1 if
|
|
|
|
/// none is found.
|
|
|
|
int findFirstPredOperandIdx() const;
|
2007-02-19 22:49:54 +01:00
|
|
|
|
2007-10-12 10:50:34 +02:00
|
|
|
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
|
|
|
|
/// to two addr elimination.
|
|
|
|
bool isRegReDefinedByTwoAddr(unsigned Reg) const;
|
|
|
|
|
2006-11-15 21:48:17 +01:00
|
|
|
/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
|
|
|
|
///
|
2006-12-06 09:27:42 +01:00
|
|
|
void copyKillDeadInfo(const MachineInstr *MI);
|
2006-11-15 21:48:17 +01:00
|
|
|
|
2007-05-15 03:26:09 +02:00
|
|
|
/// copyPredicates - Copies predicate operand(s) from MI.
|
|
|
|
void copyPredicates(const MachineInstr *MI);
|
|
|
|
|
2001-10-11 06:23:19 +02:00
|
|
|
//
|
|
|
|
// Debugging support
|
2002-10-30 01:46:48 +01:00
|
|
|
//
|
2006-12-17 06:15:13 +01:00
|
|
|
void print(std::ostream *OS, const TargetMachine *TM) const {
|
|
|
|
if (OS) print(*OS, TM);
|
2006-11-28 23:21:29 +01:00
|
|
|
}
|
2004-06-25 02:13:11 +02:00
|
|
|
void print(std::ostream &OS, const TargetMachine *TM) const;
|
2006-12-16 03:15:42 +01:00
|
|
|
void print(std::ostream &OS) const;
|
2006-12-17 06:15:13 +01:00
|
|
|
void print(std::ostream *OS) const { if (OS) print(*OS); }
|
2002-10-28 05:24:49 +01:00
|
|
|
void dump() const;
|
2006-12-16 03:15:42 +01:00
|
|
|
friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr){
|
|
|
|
minstr.print(os);
|
|
|
|
return os;
|
|
|
|
}
|
2002-02-05 07:02:59 +01:00
|
|
|
|
2002-10-28 21:48:39 +01:00
|
|
|
//===--------------------------------------------------------------------===//
|
2006-05-04 21:14:44 +02:00
|
|
|
// Accessors to add operands when building up machine instructions.
|
2002-10-28 21:48:39 +01:00
|
|
|
//
|
|
|
|
|
2006-05-04 21:14:44 +02:00
|
|
|
/// addRegOperand - Add a register operand.
|
2002-11-17 23:33:54 +01:00
|
|
|
///
|
2006-11-14 00:34:06 +01:00
|
|
|
void addRegOperand(unsigned Reg, bool IsDef, bool IsImp = false,
|
2007-11-14 08:59:08 +01:00
|
|
|
bool IsKill = false, bool IsDead = false,
|
|
|
|
unsigned SubReg = 0) {
|
2006-11-10 09:32:14 +01:00
|
|
|
MachineOperand &Op = AddNewOperand(IsImp);
|
2006-05-04 21:14:44 +02:00
|
|
|
Op.opType = MachineOperand::MO_Register;
|
2006-09-05 04:31:13 +02:00
|
|
|
Op.IsDef = IsDef;
|
2006-11-10 09:32:14 +01:00
|
|
|
Op.IsImp = IsImp;
|
2006-11-14 00:34:06 +01:00
|
|
|
Op.IsKill = IsKill;
|
|
|
|
Op.IsDead = IsDead;
|
2006-05-04 21:14:44 +02:00
|
|
|
Op.contents.RegNo = Reg;
|
2007-11-17 01:31:16 +01:00
|
|
|
Op.auxInfo.subReg = (unsigned char)SubReg;
|
2002-11-17 23:33:54 +01:00
|
|
|
}
|
|
|
|
|
2006-05-04 20:05:43 +02:00
|
|
|
/// addImmOperand - Add a zero extended constant argument to the
|
2002-10-28 21:48:39 +01:00
|
|
|
/// machine instruction.
|
|
|
|
///
|
2006-05-04 20:05:43 +02:00
|
|
|
void addImmOperand(int64_t Val) {
|
2006-05-04 21:14:44 +02:00
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_Immediate;
|
|
|
|
Op.contents.immedVal = Val;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = 0;
|
2002-10-28 21:48:39 +01:00
|
|
|
}
|
|
|
|
|
2002-12-15 09:01:02 +01:00
|
|
|
void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
|
2006-05-04 21:14:44 +02:00
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_MachineBasicBlock;
|
|
|
|
Op.contents.MBB = MBB;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = 0;
|
2002-12-15 09:01:02 +01:00
|
|
|
}
|
2002-10-28 21:48:39 +01:00
|
|
|
|
2002-12-25 06:00:49 +01:00
|
|
|
/// addFrameIndexOperand - Add an abstract frame index to the instruction
|
|
|
|
///
|
|
|
|
void addFrameIndexOperand(unsigned Idx) {
|
2006-05-04 21:14:44 +02:00
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_FrameIndex;
|
|
|
|
Op.contents.immedVal = Idx;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = 0;
|
2002-12-25 06:00:49 +01:00
|
|
|
}
|
|
|
|
|
2003-01-13 01:18:17 +01:00
|
|
|
/// addConstantPoolndexOperand - Add a constant pool object index to the
|
|
|
|
/// instruction.
|
|
|
|
///
|
2006-05-04 21:14:44 +02:00
|
|
|
void addConstantPoolIndexOperand(unsigned Idx, int Offset) {
|
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_ConstantPoolIndex;
|
|
|
|
Op.contents.immedVal = Idx;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = Offset;
|
2003-01-13 01:18:17 +01:00
|
|
|
}
|
|
|
|
|
2006-04-22 20:53:45 +02:00
|
|
|
/// addJumpTableIndexOperand - Add a jump table object index to the
|
|
|
|
/// instruction.
|
|
|
|
///
|
2006-05-04 21:14:44 +02:00
|
|
|
void addJumpTableIndexOperand(unsigned Idx) {
|
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_JumpTableIndex;
|
|
|
|
Op.contents.immedVal = Idx;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = 0;
|
2006-04-22 20:53:45 +02:00
|
|
|
}
|
|
|
|
|
2006-05-04 03:15:02 +02:00
|
|
|
void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
|
2006-05-04 21:14:44 +02:00
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_GlobalAddress;
|
|
|
|
Op.contents.GV = GV;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = Offset;
|
2003-01-13 01:18:17 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/// addExternalSymbolOperand - Add an external symbol operand to this instr
|
|
|
|
///
|
2006-05-04 03:15:02 +02:00
|
|
|
void addExternalSymbolOperand(const char *SymName) {
|
2006-05-04 21:14:44 +02:00
|
|
|
MachineOperand &Op = AddNewOperand();
|
|
|
|
Op.opType = MachineOperand::MO_ExternalSymbol;
|
|
|
|
Op.contents.SymbolName = SymName;
|
2007-05-01 07:57:02 +02:00
|
|
|
Op.auxInfo.offset = 0;
|
2003-01-13 01:18:17 +01:00
|
|
|
}
|
2002-12-28 21:05:44 +01:00
|
|
|
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
// Accessors used to modify instructions in place.
|
|
|
|
//
|
|
|
|
|
2006-11-30 08:08:44 +01:00
|
|
|
/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
|
|
|
|
/// the current instruction with a new one.
|
2003-01-13 01:18:17 +01:00
|
|
|
///
|
2006-11-30 08:08:44 +01:00
|
|
|
void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
|
2003-01-13 01:18:17 +01:00
|
|
|
|
|
|
|
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
|
|
|
|
/// fewer operand than it started with.
|
|
|
|
///
|
|
|
|
void RemoveOperand(unsigned i) {
|
2006-05-04 21:14:44 +02:00
|
|
|
Operands.erase(Operands.begin()+i);
|
|
|
|
}
|
|
|
|
private:
|
2006-11-10 09:32:14 +01:00
|
|
|
MachineOperand &AddNewOperand(bool IsImp = false) {
|
|
|
|
assert((IsImp || !OperandsComplete()) &&
|
2006-05-04 21:14:44 +02:00
|
|
|
"Trying to add an operand to a machine instr that is already done!");
|
2007-04-25 09:24:13 +02:00
|
|
|
if (IsImp || NumImplicitOps == 0) { // This is true most of the time.
|
2006-11-14 00:34:06 +01:00
|
|
|
Operands.push_back(MachineOperand());
|
|
|
|
return Operands.back();
|
|
|
|
}
|
2007-04-25 09:24:13 +02:00
|
|
|
return *Operands.insert(Operands.begin()+Operands.size()-NumImplicitOps,
|
|
|
|
MachineOperand());
|
2003-01-13 01:18:17 +01:00
|
|
|
}
|
2006-11-14 00:34:06 +01:00
|
|
|
|
|
|
|
/// addImplicitDefUseOperands - Add all implicit def and use operands to
|
|
|
|
/// this instruction.
|
2006-11-30 08:08:44 +01:00
|
|
|
void addImplicitDefUseOperands();
|
2001-10-11 06:23:19 +02:00
|
|
|
};
|
2001-07-21 14:39:03 +02:00
|
|
|
|
2003-06-03 17:42:53 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
2001-10-10 22:50:20 +02:00
|
|
|
// Debugging Support
|
|
|
|
|
2003-06-03 17:42:53 +02:00
|
|
|
std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
|
|
|
|
std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
|
2001-08-29 01:11:46 +02:00
|
|
|
|
2003-11-11 23:41:34 +01:00
|
|
|
} // End llvm namespace
|
|
|
|
|
2001-07-21 14:39:03 +02:00
|
|
|
#endif
|