2009-05-18 21:03:16 +02:00
|
|
|
//===-- llvm/CodeGen/Spiller.cpp - Spiller -------------------------------===//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#define DEBUG_TYPE "spiller"
|
|
|
|
|
|
|
|
#include "Spiller.h"
|
|
|
|
#include "VirtRegMap.h"
|
|
|
|
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
|
2012-04-03 00:44:18 +02:00
|
|
|
#include "llvm/CodeGen/LiveRangeEdit.h"
|
2010-10-26 02:11:33 +02:00
|
|
|
#include "llvm/CodeGen/LiveStackAnalysis.h"
|
2009-08-22 22:54:03 +02:00
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
2009-05-18 21:03:16 +02:00
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
2010-07-11 00:42:59 +02:00
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2010-07-21 01:50:15 +02:00
|
|
|
#include "llvm/CodeGen/MachineLoopInfo.h"
|
2009-05-18 21:03:16 +02:00
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
2009-11-19 05:15:33 +01:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2009-05-18 21:03:16 +02:00
|
|
|
#include "llvm/Support/Debug.h"
|
2010-06-26 00:53:05 +02:00
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2009-08-22 22:54:03 +02:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2009-05-18 21:03:16 +02:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2009-11-19 05:15:33 +01:00
|
|
|
namespace {
|
2011-11-13 00:29:02 +01:00
|
|
|
enum SpillerName { trivial, inline_ };
|
2009-11-19 05:15:33 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static cl::opt<SpillerName>
|
|
|
|
spillerOpt("spiller",
|
|
|
|
cl::desc("Spiller to use: (default: standard)"),
|
|
|
|
cl::Prefix,
|
2009-12-09 06:39:12 +01:00
|
|
|
cl::values(clEnumVal(trivial, "trivial spiller"),
|
2010-06-30 02:24:51 +02:00
|
|
|
clEnumValN(inline_, "inline", "inline spiller"),
|
2009-11-19 05:15:33 +01:00
|
|
|
clEnumValEnd),
|
2011-11-13 00:29:02 +01:00
|
|
|
cl::init(trivial));
|
2009-11-19 05:15:33 +01:00
|
|
|
|
2009-12-09 06:39:12 +01:00
|
|
|
// Spiller virtual destructor implementation.
|
2009-05-18 21:03:16 +02:00
|
|
|
Spiller::~Spiller() {}
|
|
|
|
|
|
|
|
namespace {
|
|
|
|
|
2009-06-02 18:53:25 +02:00
|
|
|
/// Utility class for spillers.
|
|
|
|
class SpillerBase : public Spiller {
|
|
|
|
protected:
|
2010-07-21 01:50:15 +02:00
|
|
|
MachineFunctionPass *pass;
|
2009-06-02 18:53:25 +02:00
|
|
|
MachineFunction *mf;
|
2010-07-21 01:50:15 +02:00
|
|
|
VirtRegMap *vrm;
|
2009-06-02 18:53:25 +02:00
|
|
|
LiveIntervals *lis;
|
|
|
|
MachineFrameInfo *mfi;
|
|
|
|
MachineRegisterInfo *mri;
|
|
|
|
const TargetInstrInfo *tii;
|
2010-05-06 21:06:44 +02:00
|
|
|
const TargetRegisterInfo *tri;
|
2010-07-06 20:35:20 +02:00
|
|
|
|
|
|
|
/// Construct a spiller base.
|
2010-07-21 01:50:15 +02:00
|
|
|
SpillerBase(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
|
|
|
|
: pass(&pass), mf(&mf), vrm(&vrm)
|
2009-05-18 21:03:16 +02:00
|
|
|
{
|
2010-07-21 01:50:15 +02:00
|
|
|
lis = &pass.getAnalysis<LiveIntervals>();
|
|
|
|
mfi = mf.getFrameInfo();
|
|
|
|
mri = &mf.getRegInfo();
|
|
|
|
tii = mf.getTarget().getInstrInfo();
|
|
|
|
tri = mf.getTarget().getRegisterInfo();
|
2009-05-18 21:03:16 +02:00
|
|
|
}
|
|
|
|
|
2009-06-02 18:53:25 +02:00
|
|
|
/// Add spill ranges for every use/def of the live interval, inserting loads
|
2009-11-18 21:31:20 +01:00
|
|
|
/// immediately before each use, and stores after each def. No folding or
|
|
|
|
/// remat is attempted.
|
2012-02-28 23:07:24 +01:00
|
|
|
void trivialSpillEverywhere(LiveRangeEdit& LRE) {
|
|
|
|
LiveInterval* li = &LRE.getParent();
|
|
|
|
|
2010-01-05 02:25:55 +01:00
|
|
|
DEBUG(dbgs() << "Spilling everywhere " << *li << "\n");
|
2009-05-18 21:03:16 +02:00
|
|
|
|
|
|
|
assert(li->weight != HUGE_VALF &&
|
|
|
|
"Attempting to spill already spilled value.");
|
|
|
|
|
2011-01-09 22:17:37 +01:00
|
|
|
assert(!TargetRegisterInfo::isStackSlot(li->reg) &&
|
2009-05-18 21:03:16 +02:00
|
|
|
"Trying to spill a stack slot.");
|
|
|
|
|
2010-01-05 02:25:55 +01:00
|
|
|
DEBUG(dbgs() << "Trivial spill everywhere of reg" << li->reg << "\n");
|
2009-06-24 22:46:24 +02:00
|
|
|
|
2009-05-18 21:03:16 +02:00
|
|
|
const TargetRegisterClass *trc = mri->getRegClass(li->reg);
|
|
|
|
unsigned ss = vrm->assignVirt2StackSlot(li->reg);
|
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Iterate over reg uses/defs.
|
2009-06-02 18:53:25 +02:00
|
|
|
for (MachineRegisterInfo::reg_iterator
|
|
|
|
regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
|
2009-05-18 21:03:16 +02:00
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Grab the use/def instr.
|
2009-05-18 21:03:16 +02:00
|
|
|
MachineInstr *mi = &*regItr;
|
2009-06-24 22:46:24 +02:00
|
|
|
|
2010-01-05 02:25:55 +01:00
|
|
|
DEBUG(dbgs() << " Processing " << *mi);
|
2009-06-24 22:46:24 +02:00
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Step regItr to the next use/def instr.
|
2009-06-02 18:53:25 +02:00
|
|
|
do {
|
|
|
|
++regItr;
|
|
|
|
} while (regItr != mri->reg_end() && (&*regItr == mi));
|
2010-07-06 20:35:20 +02:00
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Collect uses & defs for this instr.
|
2009-05-18 21:03:16 +02:00
|
|
|
SmallVector<unsigned, 2> indices;
|
|
|
|
bool hasUse = false;
|
|
|
|
bool hasDef = false;
|
|
|
|
for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
|
|
|
|
MachineOperand &op = mi->getOperand(i);
|
|
|
|
if (!op.isReg() || op.getReg() != li->reg)
|
|
|
|
continue;
|
|
|
|
hasUse |= mi->getOperand(i).isUse();
|
|
|
|
hasDef |= mi->getOperand(i).isDef();
|
|
|
|
indices.push_back(i);
|
|
|
|
}
|
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Create a new vreg & interval for this instr.
|
2012-04-03 00:22:53 +02:00
|
|
|
LiveInterval *newLI = &LRE.create();
|
2009-06-02 18:53:25 +02:00
|
|
|
newLI->weight = HUGE_VALF;
|
2010-07-06 20:35:20 +02:00
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Update the reg operands & kill flags.
|
2009-05-18 21:03:16 +02:00
|
|
|
for (unsigned i = 0; i < indices.size(); ++i) {
|
2009-11-18 21:31:20 +01:00
|
|
|
unsigned mopIdx = indices[i];
|
|
|
|
MachineOperand &mop = mi->getOperand(mopIdx);
|
2012-02-28 23:07:24 +01:00
|
|
|
mop.setReg(newLI->reg);
|
2009-11-18 21:31:20 +01:00
|
|
|
if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) {
|
|
|
|
mop.setIsKill(true);
|
2009-05-18 21:03:16 +02:00
|
|
|
}
|
|
|
|
}
|
2009-06-02 18:53:25 +02:00
|
|
|
assert(hasUse || hasDef);
|
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Insert reload if necessary.
|
|
|
|
MachineBasicBlock::iterator miItr(mi);
|
2009-05-18 21:03:16 +02:00
|
|
|
if (hasUse) {
|
2012-02-28 23:07:24 +01:00
|
|
|
tii->loadRegFromStackSlot(*mi->getParent(), miItr, newLI->reg, ss, trc,
|
2010-05-06 21:06:44 +02:00
|
|
|
tri);
|
2009-11-18 21:31:20 +01:00
|
|
|
MachineInstr *loadInstr(prior(miItr));
|
|
|
|
SlotIndex loadIndex =
|
2011-11-13 21:45:27 +01:00
|
|
|
lis->InsertMachineInstrInMaps(loadInstr).getRegSlot();
|
2009-11-18 21:31:20 +01:00
|
|
|
SlotIndex endIndex = loadIndex.getNextIndex();
|
|
|
|
VNInfo *loadVNI =
|
2012-02-04 06:20:49 +01:00
|
|
|
newLI->getNextValue(loadIndex, lis->getVNInfoAllocator());
|
2009-11-18 21:31:20 +01:00
|
|
|
newLI->addRange(LiveRange(loadIndex, endIndex, loadVNI));
|
2009-05-18 21:03:16 +02:00
|
|
|
}
|
|
|
|
|
2009-11-18 21:31:20 +01:00
|
|
|
// Insert store if necessary.
|
2009-05-18 21:03:16 +02:00
|
|
|
if (hasDef) {
|
2012-02-28 23:07:24 +01:00
|
|
|
tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr),newLI->reg,
|
2010-05-06 21:06:44 +02:00
|
|
|
true, ss, trc, tri);
|
2009-12-03 01:50:42 +01:00
|
|
|
MachineInstr *storeInstr(llvm::next(miItr));
|
2009-11-18 21:31:20 +01:00
|
|
|
SlotIndex storeIndex =
|
2011-11-13 21:45:27 +01:00
|
|
|
lis->InsertMachineInstrInMaps(storeInstr).getRegSlot();
|
2009-11-18 21:31:20 +01:00
|
|
|
SlotIndex beginIndex = storeIndex.getPrevIndex();
|
|
|
|
VNInfo *storeVNI =
|
2012-02-04 06:20:49 +01:00
|
|
|
newLI->getNextValue(beginIndex, lis->getVNInfoAllocator());
|
2009-11-18 21:31:20 +01:00
|
|
|
newLI->addRange(LiveRange(beginIndex, storeIndex, storeVNI));
|
2009-05-18 21:03:16 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2009-06-02 18:53:25 +02:00
|
|
|
};
|
2009-05-18 21:03:16 +02:00
|
|
|
|
2010-04-08 00:44:07 +02:00
|
|
|
} // end anonymous namespace
|
|
|
|
|
|
|
|
namespace {
|
2009-05-18 21:03:16 +02:00
|
|
|
|
2009-06-02 18:53:25 +02:00
|
|
|
/// Spills any live range using the spill-everywhere method with no attempt at
|
|
|
|
/// folding.
|
|
|
|
class TrivialSpiller : public SpillerBase {
|
|
|
|
public:
|
2009-06-19 04:17:53 +02:00
|
|
|
|
2010-07-21 01:50:15 +02:00
|
|
|
TrivialSpiller(MachineFunctionPass &pass, MachineFunction &mf,
|
|
|
|
VirtRegMap &vrm)
|
|
|
|
: SpillerBase(pass, mf, vrm) {}
|
2009-05-18 21:03:16 +02:00
|
|
|
|
2011-03-10 02:51:42 +01:00
|
|
|
void spill(LiveRangeEdit &LRE) {
|
2009-11-19 05:15:33 +01:00
|
|
|
// Ignore spillIs - we don't use it.
|
2012-02-28 23:07:24 +01:00
|
|
|
trivialSpillEverywhere(LRE);
|
2009-05-18 21:03:16 +02:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2010-04-08 00:44:07 +02:00
|
|
|
} // end anonymous namespace
|
|
|
|
|
2011-12-20 03:50:00 +01:00
|
|
|
void Spiller::anchor() { }
|
|
|
|
|
2010-07-21 01:50:15 +02:00
|
|
|
llvm::Spiller* llvm::createSpiller(MachineFunctionPass &pass,
|
|
|
|
MachineFunction &mf,
|
|
|
|
VirtRegMap &vrm) {
|
2009-11-19 05:15:33 +01:00
|
|
|
switch (spillerOpt) {
|
2010-07-21 01:50:15 +02:00
|
|
|
case trivial: return new TrivialSpiller(pass, mf, vrm);
|
|
|
|
case inline_: return createInlineSpiller(pass, mf, vrm);
|
2009-11-19 05:15:33 +01:00
|
|
|
}
|
2012-01-10 19:08:01 +01:00
|
|
|
llvm_unreachable("Invalid spiller optimization");
|
2009-05-18 21:03:16 +02:00
|
|
|
}
|