llvm-mirror/docs/AMDGPU/gfx10_ssrc64_1.rst

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.. _amdgpu_synid10_ssrc64_1:

ssrc
===========================

Instruction input.

*Size:* 2 dwords.

*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of GFX10; - added description of operands sccz, vccz, lds_direct, etc; - minor bugfixing and improvements. llvm-svn: 365347 2019-07-08 18:50:11 +02:00			`..`
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			`.. _amdgpu_synid10_ssrc64_1:`

			`ssrc`
			`===========================`

			`Instruction input.`

			`Size: 2 dwords.`

[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. Summary of changes: - added description of MTBUF instructions and format modifier; - described limitations of f16 inline constants when used with integer operands; - updated description of gfx9+ flat global addressing modes; - v_accvgpr_write_b32 src0 corrections (gfx908); - minor bugfixing and improvements. 2020-08-21 13:22:25 +02:00			Operands: :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`