2012-02-18 13:03:15 +01:00
|
|
|
//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
|
2009-07-08 19:28:55 +02:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This file contains the base ARM implementation of TargetRegisterInfo class.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2012-03-17 08:33:42 +01:00
|
|
|
#include "ARMBaseRegisterInfo.h"
|
2009-07-08 19:28:55 +02:00
|
|
|
#include "ARM.h"
|
2009-07-08 20:31:39 +02:00
|
|
|
#include "ARMBaseInstrInfo.h"
|
2011-01-10 13:39:04 +01:00
|
|
|
#include "ARMFrameLowering.h"
|
2009-07-08 19:28:55 +02:00
|
|
|
#include "ARMMachineFunctionInfo.h"
|
|
|
|
#include "ARMSubtarget.h"
|
2011-07-21 01:34:39 +02:00
|
|
|
#include "MCTargetDesc/ARMAddressingModes.h"
|
2012-12-03 17:50:05 +01:00
|
|
|
#include "llvm/ADT/BitVector.h"
|
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2009-07-08 19:28:55 +02:00
|
|
|
#include "llvm/CodeGen/MachineConstantPool.h"
|
|
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
#include "llvm/CodeGen/RegisterScavenging.h"
|
2012-12-03 23:35:35 +01:00
|
|
|
#include "llvm/CodeGen/VirtRegMap.h"
|
2013-01-02 12:36:10 +01:00
|
|
|
#include "llvm/IR/Constants.h"
|
|
|
|
#include "llvm/IR/DerivedTypes.h"
|
|
|
|
#include "llvm/IR/Function.h"
|
|
|
|
#include "llvm/IR/LLVMContext.h"
|
2009-10-27 23:45:39 +01:00
|
|
|
#include "llvm/Support/Debug.h"
|
2009-07-08 20:01:40 +02:00
|
|
|
#include "llvm/Support/ErrorHandling.h"
|
2009-07-08 22:53:28 +02:00
|
|
|
#include "llvm/Support/raw_ostream.h"
|
2011-01-10 13:39:04 +01:00
|
|
|
#include "llvm/Target/TargetFrameLowering.h"
|
2009-07-08 19:28:55 +02:00
|
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
#include "llvm/Target/TargetOptions.h"
|
2011-06-27 20:32:37 +02:00
|
|
|
|
2014-07-16 22:13:31 +02:00
|
|
|
#define DEBUG_TYPE "arm-register-info"
|
|
|
|
|
2011-06-27 20:32:37 +02:00
|
|
|
#define GET_REGINFO_TARGET_DESC
|
2011-06-24 03:44:41 +02:00
|
|
|
#include "ARMGenRegisterInfo.inc"
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2010-11-18 02:28:51 +01:00
|
|
|
using namespace llvm;
|
|
|
|
|
2013-06-07 07:54:19 +02:00
|
|
|
ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti)
|
2014-05-18 06:12:52 +02:00
|
|
|
: ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) {
|
2014-05-30 15:23:06 +02:00
|
|
|
if (STI.isTargetMachO()) {
|
|
|
|
if (STI.isTargetDarwin() || STI.isThumb1Only())
|
|
|
|
FramePtr = ARM::R7;
|
|
|
|
else
|
|
|
|
FramePtr = ARM::R11;
|
|
|
|
} else if (STI.isTargetWindows())
|
2014-05-18 06:12:52 +02:00
|
|
|
FramePtr = ARM::R11;
|
|
|
|
else // ARM EABI
|
|
|
|
FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11;
|
2009-07-08 19:28:55 +02:00
|
|
|
}
|
|
|
|
|
2014-04-04 07:16:06 +02:00
|
|
|
const MCPhysReg*
|
2009-07-08 19:28:55 +02:00
|
|
|
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
|
2014-12-11 19:49:37 +01:00
|
|
|
const MCPhysReg *RegList =
|
|
|
|
STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
|
2013-10-01 16:33:28 +02:00
|
|
|
|
|
|
|
if (!MF) return RegList;
|
|
|
|
|
|
|
|
const Function *F = MF->getFunction();
|
|
|
|
if (F->getCallingConv() == CallingConv::GHC) {
|
2013-07-04 01:39:13 +02:00
|
|
|
// GHC set of callee saved regs is empty as all those regs are
|
|
|
|
// used for passing STG regs around
|
|
|
|
return CSR_NoRegs_SaveList;
|
2013-10-01 16:33:28 +02:00
|
|
|
} else if (F->hasFnAttribute("interrupt")) {
|
|
|
|
if (STI.isMClass()) {
|
|
|
|
// M-class CPUs have hardware which saves the registers needed to allow a
|
|
|
|
// function conforming to the AAPCS to function as a handler.
|
|
|
|
return CSR_AAPCS_SaveList;
|
|
|
|
} else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
|
|
|
|
// Fast interrupt mode gives the handler a private copy of R8-R14, so less
|
|
|
|
// need to be saved to restore user-mode state.
|
|
|
|
return CSR_FIQ_SaveList;
|
|
|
|
} else {
|
|
|
|
// Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
|
|
|
|
// exception handling.
|
|
|
|
return CSR_GenericInt_SaveList;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return RegList;
|
2012-01-18 00:09:00 +01:00
|
|
|
}
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2012-01-18 00:09:00 +01:00
|
|
|
const uint32_t*
|
2013-07-04 01:39:13 +02:00
|
|
|
ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
|
|
|
|
if (CC == CallingConv::GHC)
|
|
|
|
// This is academic becase all GHC calls are (supposed to be) tail calls
|
|
|
|
return CSR_NoRegs_RegMask;
|
2014-12-11 19:49:37 +01:00
|
|
|
return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
|
2009-07-08 19:28:55 +02:00
|
|
|
}
|
|
|
|
|
2013-04-20 07:14:40 +02:00
|
|
|
const uint32_t*
|
2013-06-27 00:27:50 +02:00
|
|
|
ARMBaseRegisterInfo::getNoPreservedMask() const {
|
|
|
|
return CSR_NoRegs_RegMask;
|
2013-04-20 07:14:40 +02:00
|
|
|
}
|
|
|
|
|
2012-11-07 00:05:24 +01:00
|
|
|
const uint32_t*
|
2013-07-04 01:39:13 +02:00
|
|
|
ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const {
|
2013-06-27 00:27:50 +02:00
|
|
|
// This should return a register mask that is the same as that returned by
|
|
|
|
// getCallPreservedMask but that additionally preserves the register used for
|
|
|
|
// the first i32 argument (which must also be the register used to return a
|
|
|
|
// single i32 return value)
|
|
|
|
//
|
|
|
|
// In case that the calling convention does not use the same register for
|
2013-07-04 01:39:13 +02:00
|
|
|
// both or otherwise does not want to enable this optimization, the function
|
|
|
|
// should return NULL
|
|
|
|
if (CC == CallingConv::GHC)
|
|
|
|
// This is academic becase all GHC calls are (supposed to be) tail calls
|
2014-04-25 07:30:21 +02:00
|
|
|
return nullptr;
|
2014-12-11 19:49:37 +01:00
|
|
|
return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
|
|
|
|
: CSR_AAPCS_ThisReturn_RegMask;
|
2012-11-07 00:05:24 +01:00
|
|
|
}
|
|
|
|
|
2010-01-07 00:54:42 +01:00
|
|
|
BitVector ARMBaseRegisterInfo::
|
|
|
|
getReservedRegs(const MachineFunction &MF) const {
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
2010-11-18 22:19:35 +01:00
|
|
|
|
2011-04-15 07:18:47 +02:00
|
|
|
// FIXME: avoid re-calculating this every time.
|
2009-07-08 19:28:55 +02:00
|
|
|
BitVector Reserved(getNumRegs());
|
|
|
|
Reserved.set(ARM::SP);
|
|
|
|
Reserved.set(ARM::PC);
|
2012-03-06 01:19:55 +01:00
|
|
|
Reserved.set(ARM::FPSCR);
|
2013-05-13 16:10:04 +02:00
|
|
|
Reserved.set(ARM::APSR_NZCV);
|
2010-11-18 22:19:35 +01:00
|
|
|
if (TFI->hasFP(MF))
|
2009-07-08 19:28:55 +02:00
|
|
|
Reserved.set(FramePtr);
|
2010-09-03 20:37:12 +02:00
|
|
|
if (hasBasePointer(MF))
|
|
|
|
Reserved.set(BasePtr);
|
2009-07-08 19:28:55 +02:00
|
|
|
// Some targets reserve R9.
|
|
|
|
if (STI.isR9Reserved())
|
|
|
|
Reserved.set(ARM::R9);
|
2011-06-18 02:53:27 +02:00
|
|
|
// Reserve D16-D31 if the subtarget doesn't support them.
|
|
|
|
if (!STI.hasVFP3() || STI.hasD16()) {
|
|
|
|
assert(ARM::D31 == ARM::D16 + 15);
|
|
|
|
for (unsigned i = 0; i != 16; ++i)
|
|
|
|
Reserved.set(ARM::D16 + i);
|
|
|
|
}
|
2012-10-26 23:29:15 +02:00
|
|
|
const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
|
|
|
|
for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
|
|
|
|
for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
|
|
|
|
if (Reserved.test(*SI)) Reserved.set(*I);
|
|
|
|
|
2009-07-08 19:28:55 +02:00
|
|
|
return Reserved;
|
|
|
|
}
|
|
|
|
|
2011-04-26 20:52:33 +02:00
|
|
|
const TargetRegisterClass*
|
|
|
|
ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
|
|
|
|
const {
|
|
|
|
const TargetRegisterClass *Super = RC;
|
2011-10-01 00:19:07 +02:00
|
|
|
TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
|
2011-04-26 20:52:33 +02:00
|
|
|
do {
|
|
|
|
switch (Super->getID()) {
|
|
|
|
case ARM::GPRRegClassID:
|
|
|
|
case ARM::SPRRegClassID:
|
|
|
|
case ARM::DPRRegClassID:
|
|
|
|
case ARM::QPRRegClassID:
|
|
|
|
case ARM::QQPRRegClassID:
|
|
|
|
case ARM::QQQQPRRegClassID:
|
2012-10-26 23:29:15 +02:00
|
|
|
case ARM::GPRPairRegClassID:
|
2011-04-26 20:52:33 +02:00
|
|
|
return Super;
|
|
|
|
}
|
|
|
|
Super = *I++;
|
|
|
|
} while (Super);
|
|
|
|
return RC;
|
|
|
|
}
|
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.
e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12
After REG_SEQUENCE is eliminated, we are left with:
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.
llvm-svn: 103835
2010-05-15 01:21:14 +02:00
|
|
|
|
2009-07-29 22:31:52 +02:00
|
|
|
const TargetRegisterClass *
|
2012-05-08 00:10:26 +02:00
|
|
|
ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
|
|
|
|
const {
|
2012-04-20 09:30:17 +02:00
|
|
|
return &ARM::GPRRegClass;
|
2009-07-08 19:28:55 +02:00
|
|
|
}
|
2011-03-07 22:56:36 +01:00
|
|
|
|
2011-08-30 03:34:54 +02:00
|
|
|
const TargetRegisterClass *
|
|
|
|
ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
|
|
|
if (RC == &ARM::CCRRegClass)
|
2014-10-01 21:21:03 +02:00
|
|
|
return &ARM::rGPRRegClass; // Can't copy CCR registers.
|
2011-08-30 03:34:54 +02:00
|
|
|
return RC;
|
|
|
|
}
|
|
|
|
|
2011-03-07 22:56:36 +01:00
|
|
|
unsigned
|
|
|
|
ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
|
|
|
|
MachineFunction &MF) const {
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
2011-03-07 22:56:36 +01:00
|
|
|
|
|
|
|
switch (RC->getID()) {
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
case ARM::tGPRRegClassID:
|
|
|
|
return TFI->hasFP(MF) ? 4 : 5;
|
|
|
|
case ARM::GPRRegClassID: {
|
|
|
|
unsigned FP = TFI->hasFP(MF) ? 1 : 0;
|
|
|
|
return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
|
|
|
|
}
|
|
|
|
case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
|
|
|
|
case ARM::DPRRegClassID:
|
|
|
|
return 32 - 10;
|
|
|
|
}
|
|
|
|
}
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2012-12-03 23:35:35 +01:00
|
|
|
// Get the other register in a GPRPair.
|
|
|
|
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
|
|
|
|
for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
|
|
|
|
if (ARM::GPRPairRegClass.contains(*Supers))
|
|
|
|
return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Resolve the RegPairEven / RegPairOdd register allocator hints.
|
|
|
|
void
|
|
|
|
ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
|
|
|
|
ArrayRef<MCPhysReg> Order,
|
|
|
|
SmallVectorImpl<MCPhysReg> &Hints,
|
|
|
|
const MachineFunction &MF,
|
|
|
|
const VirtRegMap *VRM) const {
|
|
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
|
|
|
|
|
|
|
|
unsigned Odd;
|
|
|
|
switch (Hint.first) {
|
|
|
|
case ARMRI::RegPairEven:
|
|
|
|
Odd = 0;
|
|
|
|
break;
|
|
|
|
case ARMRI::RegPairOdd:
|
|
|
|
Odd = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// This register should preferably be even (Odd == 0) or odd (Odd == 1).
|
|
|
|
// Check if the other part of the pair has already been assigned, and provide
|
|
|
|
// the paired register as the first hint.
|
|
|
|
unsigned PairedPhys = 0;
|
|
|
|
if (VRM && VRM->hasPhys(Hint.second)) {
|
|
|
|
PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
|
|
|
|
if (PairedPhys && MRI.isReserved(PairedPhys))
|
|
|
|
PairedPhys = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// First prefer the paired physreg.
|
2013-02-19 19:55:36 +01:00
|
|
|
if (PairedPhys &&
|
|
|
|
std::find(Order.begin(), Order.end(), PairedPhys) != Order.end())
|
2012-12-03 23:35:35 +01:00
|
|
|
Hints.push_back(PairedPhys);
|
|
|
|
|
|
|
|
// Then prefer even or odd registers.
|
|
|
|
for (unsigned I = 0, E = Order.size(); I != E; ++I) {
|
|
|
|
unsigned Reg = Order[I];
|
|
|
|
if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
|
|
|
|
continue;
|
|
|
|
// Don't provide hints that are paired to a reserved register.
|
|
|
|
unsigned Paired = getPairedGPR(Reg, !Odd, this);
|
|
|
|
if (!Paired || MRI.isReserved(Paired))
|
|
|
|
continue;
|
|
|
|
Hints.push_back(Reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-07-08 19:28:55 +02:00
|
|
|
void
|
|
|
|
ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
|
|
|
|
MachineFunction &MF) const {
|
|
|
|
MachineRegisterInfo *MRI = &MF.getRegInfo();
|
|
|
|
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
|
|
|
|
if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
|
|
|
|
Hint.first == (unsigned)ARMRI::RegPairEven) &&
|
2011-01-10 03:58:51 +01:00
|
|
|
TargetRegisterInfo::isVirtualRegister(Hint.second)) {
|
2009-07-08 19:28:55 +02:00
|
|
|
// If 'Reg' is one of the even / odd register pair and it's now changed
|
|
|
|
// (e.g. coalesced) into a different register. The other register of the
|
|
|
|
// pair allocation hint must be updated to reflect the relationship
|
|
|
|
// change.
|
|
|
|
unsigned OtherReg = Hint.second;
|
|
|
|
Hint = MRI->getRegAllocationHint(OtherReg);
|
|
|
|
if (Hint.second == Reg)
|
|
|
|
// Make sure the pair has not already divorced.
|
|
|
|
MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
|
|
|
|
}
|
|
|
|
}
|
2011-04-19 20:11:45 +02:00
|
|
|
|
|
|
|
bool
|
|
|
|
ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
|
|
|
|
// CortexA9 has a Write-after-write hazard for NEON registers.
|
2012-09-13 17:05:10 +02:00
|
|
|
if (!STI.isLikeA9())
|
2011-04-19 20:11:45 +02:00
|
|
|
return false;
|
|
|
|
|
|
|
|
switch (RC->getID()) {
|
|
|
|
case ARM::DPRRegClassID:
|
|
|
|
case ARM::DPR_8RegClassID:
|
|
|
|
case ARM::DPR_VFP2RegClassID:
|
|
|
|
case ARM::QPRRegClassID:
|
|
|
|
case ARM::QPR_8RegClassID:
|
|
|
|
case ARM::QPR_VFP2RegClassID:
|
|
|
|
case ARM::SPRRegClassID:
|
|
|
|
case ARM::SPR_8RegClassID:
|
|
|
|
// Avoid reusing S, D, and Q registers.
|
|
|
|
// Don't increase register pressure for QQ and QQQQ.
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2009-07-08 19:28:55 +02:00
|
|
|
|
2010-09-03 20:37:12 +02:00
|
|
|
bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
|
2010-09-03 17:26:42 +02:00
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
2010-09-03 00:29:01 +02:00
|
|
|
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
2010-09-03 20:37:12 +02:00
|
|
|
|
2012-02-28 02:15:01 +01:00
|
|
|
// When outgoing call frames are so large that we adjust the stack pointer
|
|
|
|
// around the call, we can no longer use the stack pointer to reach the
|
|
|
|
// emergency spill slot.
|
2012-03-20 20:28:22 +01:00
|
|
|
if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
|
2010-09-03 20:37:12 +02:00
|
|
|
return true;
|
|
|
|
|
|
|
|
// Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
|
|
|
|
// negative range for ldr/str (255), and thumb1 is positive offsets only.
|
|
|
|
// It's going to be better to use the SP or Base Pointer instead. When there
|
|
|
|
// are variable sized objects, we can't reference off of the SP, so we
|
|
|
|
// reserve a Base Pointer.
|
|
|
|
if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
|
|
|
|
// Conservatively estimate whether the negative offset from the frame
|
|
|
|
// pointer will be sufficient to reach. If a function has a smallish
|
|
|
|
// frame, it's less likely to have lots of spills and callee saved
|
|
|
|
// space, so it's all more likely to be within range of the frame pointer.
|
|
|
|
// If it's wrong, the scavenger will still enable access to work, it just
|
|
|
|
// won't be optimal.
|
|
|
|
if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
|
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
|
2012-01-05 01:26:52 +01:00
|
|
|
const MachineRegisterInfo *MRI = &MF.getRegInfo();
|
2011-10-20 02:07:12 +02:00
|
|
|
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
2010-09-08 19:22:12 +02:00
|
|
|
// We can't realign the stack if:
|
|
|
|
// 1. Dynamic stack realignment is explicitly disabled,
|
2011-10-20 02:07:12 +02:00
|
|
|
// 2. This is a Thumb1 function (it's not useful, so we don't bother), or
|
|
|
|
// 3. There are VLAs in the function and the base pointer is disabled.
|
2013-08-01 23:42:05 +02:00
|
|
|
if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
|
2012-01-05 01:26:52 +01:00
|
|
|
return false;
|
|
|
|
if (AFI->isThumb1OnlyFunction())
|
|
|
|
return false;
|
|
|
|
// Stack realignment requires a frame pointer. If we already started
|
|
|
|
// register allocation with frame pointer elimination, it is too late now.
|
|
|
|
if (!MRI->canReserveReg(FramePtr))
|
|
|
|
return false;
|
2012-03-20 20:28:25 +01:00
|
|
|
// We may also need a base pointer if there are dynamic allocas or stack
|
|
|
|
// pointer adjustments around calls.
|
2015-01-29 01:19:33 +01:00
|
|
|
if (MF.getSubtarget().getFrameLowering()->hasReservedCallFrame(MF))
|
2012-01-05 01:26:52 +01:00
|
|
|
return true;
|
|
|
|
// A base pointer is required and allowed. Check that it isn't too late to
|
|
|
|
// reserve it.
|
|
|
|
return MRI->canReserveReg(BasePtr);
|
2010-01-19 19:31:11 +01:00
|
|
|
}
|
|
|
|
|
2009-10-27 23:45:39 +01:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
needsStackRealignment(const MachineFunction &MF) const {
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
2010-07-17 02:27:24 +02:00
|
|
|
const Function *F = MF.getFunction();
|
2015-01-29 01:19:33 +01:00
|
|
|
unsigned StackAlign =
|
|
|
|
MF.getSubtarget().getFrameLowering()->getStackAlignment();
|
2012-10-09 09:45:08 +02:00
|
|
|
bool requiresRealignment =
|
|
|
|
((MFI->getMaxAlignment() > StackAlign) ||
|
2012-12-30 11:32:01 +01:00
|
|
|
F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
|
|
|
|
Attribute::StackAlignment));
|
2010-09-02 21:52:39 +02:00
|
|
|
|
2010-07-17 02:27:24 +02:00
|
|
|
return requiresRealignment && canRealignStack(MF);
|
2009-10-27 23:45:39 +01:00
|
|
|
}
|
|
|
|
|
2010-01-07 00:54:42 +01:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
cannotEliminateFrame(const MachineFunction &MF) const {
|
2009-08-14 22:48:13 +02:00
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
2011-12-02 23:16:29 +01:00
|
|
|
if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
|
2009-08-14 22:48:13 +02:00
|
|
|
return true;
|
2009-11-08 01:27:19 +01:00
|
|
|
return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
|
|
|
|
|| needsStackRealignment(MF);
|
2009-08-14 22:48:13 +02:00
|
|
|
}
|
|
|
|
|
2010-09-02 21:52:39 +02:00
|
|
|
unsigned
|
2009-11-12 21:49:22 +01:00
|
|
|
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
2010-11-18 22:19:35 +01:00
|
|
|
|
|
|
|
if (TFI->hasFP(MF))
|
2009-07-08 19:28:55 +02:00
|
|
|
return FramePtr;
|
|
|
|
return ARM::SP;
|
|
|
|
}
|
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
|
|
/// specified immediate.
|
|
|
|
void ARMBaseRegisterInfo::
|
|
|
|
emitLoadConstPool(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
2009-07-08 22:28:28 +02:00
|
|
|
DebugLoc dl,
|
2009-07-16 11:20:10 +02:00
|
|
|
unsigned DestReg, unsigned SubIdx, int Val,
|
2009-07-08 20:31:39 +02:00
|
|
|
ARMCC::CondCodes Pred,
|
2011-03-05 19:43:50 +01:00
|
|
|
unsigned PredReg, unsigned MIFlags) const {
|
2009-07-08 20:31:39 +02:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
2009-07-08 20:31:39 +02:00
|
|
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
2010-04-15 03:51:59 +02:00
|
|
|
const Constant *C =
|
2009-08-13 23:58:54 +02:00
|
|
|
ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
|
2009-07-08 20:31:39 +02:00
|
|
|
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
|
|
|
|
2009-07-16 11:20:10 +02:00
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
|
|
|
|
.addReg(DestReg, getDefRegState(true), SubIdx)
|
2009-07-08 20:31:39 +02:00
|
|
|
.addConstantPoolIndex(Idx)
|
2011-03-05 19:43:50 +01:00
|
|
|
.addImm(0).addImm(Pred).addReg(PredReg)
|
|
|
|
.setMIFlags(MIFlags);
|
2009-07-08 20:31:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
|
|
return true;
|
|
|
|
}
|
2009-10-22 01:40:56 +02:00
|
|
|
|
2012-04-23 23:39:35 +02:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2009-10-20 03:26:58 +02:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
2009-10-28 18:33:28 +01:00
|
|
|
return true;
|
2009-10-20 03:26:58 +02:00
|
|
|
}
|
2009-07-08 20:31:39 +02:00
|
|
|
|
2010-08-24 21:05:43 +02:00
|
|
|
bool ARMBaseRegisterInfo::
|
|
|
|
requiresVirtualBaseRegisters(const MachineFunction &MF) const {
|
2012-12-12 00:31:12 +01:00
|
|
|
return true;
|
2010-08-24 21:05:43 +02:00
|
|
|
}
|
|
|
|
|
2010-08-20 01:52:25 +02:00
|
|
|
int64_t ARMBaseRegisterInfo::
|
2010-08-26 23:56:30 +02:00
|
|
|
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
|
2011-06-28 21:10:37 +02:00
|
|
|
const MCInstrDesc &Desc = MI->getDesc();
|
2010-08-20 01:52:25 +02:00
|
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
2012-02-22 18:25:00 +01:00
|
|
|
int64_t InstrOffs = 0;
|
2010-08-20 01:52:25 +02:00
|
|
|
int Scale = 1;
|
|
|
|
unsigned ImmIdx = 0;
|
2010-08-26 23:56:30 +02:00
|
|
|
switch (AddrMode) {
|
2010-08-20 01:52:25 +02:00
|
|
|
case ARMII::AddrModeT2_i8:
|
|
|
|
case ARMII::AddrModeT2_i12:
|
2010-10-27 00:37:02 +02:00
|
|
|
case ARMII::AddrMode_i12:
|
2010-08-20 01:52:25 +02:00
|
|
|
InstrOffs = MI->getOperand(Idx+1).getImm();
|
|
|
|
Scale = 1;
|
|
|
|
break;
|
|
|
|
case ARMII::AddrMode5: {
|
|
|
|
// VFP address mode.
|
|
|
|
const MachineOperand &OffOp = MI->getOperand(Idx+1);
|
2010-08-25 21:11:34 +02:00
|
|
|
InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
|
2010-08-20 01:52:25 +02:00
|
|
|
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs = -InstrOffs;
|
|
|
|
Scale = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARMII::AddrMode2: {
|
|
|
|
ImmIdx = Idx+2;
|
|
|
|
InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
|
|
|
|
if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs = -InstrOffs;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARMII::AddrMode3: {
|
|
|
|
ImmIdx = Idx+2;
|
|
|
|
InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
|
|
|
|
if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
|
|
InstrOffs = -InstrOffs;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARMII::AddrModeT1_s: {
|
|
|
|
ImmIdx = Idx+1;
|
|
|
|
InstrOffs = MI->getOperand(ImmIdx).getImm();
|
|
|
|
Scale = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
|
|
}
|
|
|
|
|
|
|
|
return InstrOffs * Scale;
|
|
|
|
}
|
|
|
|
|
2010-08-17 20:13:53 +02:00
|
|
|
/// needsFrameBaseReg - Returns true if the instruction's frame index
|
|
|
|
/// reference would be better served by a base register other than FP
|
|
|
|
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
|
|
|
|
/// references it should create new base registers for.
|
|
|
|
bool ARMBaseRegisterInfo::
|
2010-08-24 23:19:33 +02:00
|
|
|
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
|
|
|
|
for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
|
|
|
|
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
2010-08-17 20:13:53 +02:00
|
|
|
|
|
|
|
// It's the load/store FI references that cause issues, as it can be difficult
|
|
|
|
// to materialize the offset if it won't fit in the literal field. Estimate
|
|
|
|
// based on the size of the local frame and some conservative assumptions
|
|
|
|
// about the rest of the stack frame (note, this is pre-regalloc, so
|
|
|
|
// we don't know everything for certain yet) whether this offset is likely
|
|
|
|
// to be out of range of the immediate. Return true if so.
|
|
|
|
|
2010-08-24 20:04:52 +02:00
|
|
|
// We only generate virtual base registers for loads and stores, so
|
|
|
|
// return false for everything else.
|
2010-08-17 20:13:53 +02:00
|
|
|
unsigned Opc = MI->getOpcode();
|
|
|
|
switch (Opc) {
|
2012-08-28 05:11:27 +02:00
|
|
|
case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
|
2010-10-28 01:12:14 +02:00
|
|
|
case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
|
2012-08-28 05:11:27 +02:00
|
|
|
case ARM::t2LDRi12: case ARM::t2LDRi8:
|
|
|
|
case ARM::t2STRi12: case ARM::t2STRi8:
|
2010-08-17 20:13:53 +02:00
|
|
|
case ARM::VLDRS: case ARM::VLDRD:
|
|
|
|
case ARM::VSTRS: case ARM::VSTRD:
|
2010-08-19 19:52:13 +02:00
|
|
|
case ARM::tSTRspi: case ARM::tLDRspi:
|
2010-08-24 20:04:52 +02:00
|
|
|
break;
|
2010-08-17 20:13:53 +02:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2010-08-24 20:04:52 +02:00
|
|
|
|
|
|
|
// Without a virtual base register, if the function has variable sized
|
|
|
|
// objects, all fixed-size local references will be via the frame pointer,
|
2010-08-24 23:19:33 +02:00
|
|
|
// Approximate the offset and see if it's legal for the instruction.
|
|
|
|
// Note that the incoming offset is based on the SP value at function entry,
|
|
|
|
// so it'll be negative.
|
|
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
|
2010-08-24 23:19:33 +02:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
|
|
|
|
// Estimate an offset from the frame pointer.
|
|
|
|
// Conservatively assume all callee-saved registers get pushed. R4-R6
|
|
|
|
// will be earlier than the FP, so we ignore those.
|
|
|
|
// R7, LR
|
|
|
|
int64_t FPOffset = Offset - 8;
|
|
|
|
// ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
|
|
|
|
if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
|
|
|
|
FPOffset -= 80;
|
|
|
|
// Estimate an offset from the stack pointer.
|
2010-08-31 20:52:31 +02:00
|
|
|
// The incoming offset is relating to the SP at the start of the function,
|
|
|
|
// but when we access the local it'll be relative to the SP after local
|
|
|
|
// allocation, so adjust our SP-relative offset by that allocation size.
|
2010-08-24 23:19:33 +02:00
|
|
|
Offset = -Offset;
|
2010-08-31 20:52:31 +02:00
|
|
|
Offset += MFI->getLocalFrameSize();
|
2010-08-24 23:19:33 +02:00
|
|
|
// Assume that we'll have at least some spill slots allocated.
|
|
|
|
// FIXME: This is a total SWAG number. We should run some statistics
|
|
|
|
// and pick a real one.
|
|
|
|
Offset += 128; // 128 bytes of spill slots
|
|
|
|
|
|
|
|
// If there is a frame pointer, try using it.
|
|
|
|
// The FP is only available if there is no dynamic realignment. We
|
|
|
|
// don't know for sure yet whether we'll need that, so we guess based
|
|
|
|
// on whether there are any local variables that would trigger it.
|
2011-01-10 13:39:04 +01:00
|
|
|
unsigned StackAlign = TFI->getStackAlignment();
|
2010-11-18 22:19:35 +01:00
|
|
|
if (TFI->hasFP(MF) &&
|
2010-08-24 23:19:33 +02:00
|
|
|
!((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
|
|
|
|
if (isFrameOffsetLegal(MI, FPOffset))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// If we can reference via the stack pointer, try that.
|
|
|
|
// FIXME: This (and the code that resolves the references) can be improved
|
|
|
|
// to only disallow SP relative references in the live range of
|
|
|
|
// the VLA(s). In practice, it's unclear how much difference that
|
|
|
|
// would make, but it may be worth doing.
|
|
|
|
if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
|
|
|
|
return false;
|
2010-08-24 20:04:52 +02:00
|
|
|
|
2010-08-24 23:19:33 +02:00
|
|
|
// The offset likely isn't legal, we want to allocate a virtual base register.
|
2010-08-24 20:04:52 +02:00
|
|
|
return true;
|
2010-08-17 20:13:53 +02:00
|
|
|
}
|
|
|
|
|
2010-12-18 00:09:14 +01:00
|
|
|
/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
|
|
|
|
/// be a pointer to FrameIdx at the beginning of the basic block.
|
2010-08-18 00:41:55 +02:00
|
|
|
void ARMBaseRegisterInfo::
|
2010-12-18 00:09:14 +01:00
|
|
|
materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
|
|
|
unsigned BaseReg, int FrameIdx,
|
|
|
|
int64_t Offset) const {
|
|
|
|
ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
|
2010-08-19 19:52:13 +02:00
|
|
|
unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
|
2014-10-20 23:28:41 +02:00
|
|
|
(AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
|
2010-08-18 00:41:55 +02:00
|
|
|
|
2010-12-18 00:09:14 +01:00
|
|
|
MachineBasicBlock::iterator Ins = MBB->begin();
|
|
|
|
DebugLoc DL; // Defaults to "unknown"
|
|
|
|
if (Ins != MBB->end())
|
|
|
|
DL = Ins->getDebugLoc();
|
|
|
|
|
2012-05-08 00:10:26 +02:00
|
|
|
const MachineFunction &MF = *MBB->getParent();
|
2013-06-07 07:54:19 +02:00
|
|
|
MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
|
2014-08-05 04:39:49 +02:00
|
|
|
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
2013-06-07 07:54:19 +02:00
|
|
|
const MCInstrDesc &MCID = TII.get(ADDriOpc);
|
2012-05-08 00:10:26 +02:00
|
|
|
MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
|
2011-05-19 04:18:27 +02:00
|
|
|
|
2014-10-20 23:28:41 +02:00
|
|
|
MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
|
|
|
|
.addFrameIndex(FrameIdx).addImm(Offset);
|
2010-12-18 00:09:14 +01:00
|
|
|
|
2010-08-19 19:52:13 +02:00
|
|
|
if (!AFI->isThumb1OnlyFunction())
|
2014-10-20 23:28:41 +02:00
|
|
|
AddDefaultCC(AddDefaultPred(MIB));
|
2010-08-18 00:41:55 +02:00
|
|
|
}
|
|
|
|
|
2014-04-02 21:28:18 +02:00
|
|
|
void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
|
|
|
|
int64_t Offset) const {
|
2010-08-18 00:41:55 +02:00
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2013-06-07 07:54:19 +02:00
|
|
|
const ARMBaseInstrInfo &TII =
|
2014-08-05 04:39:49 +02:00
|
|
|
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
|
2010-08-18 00:41:55 +02:00
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
int Off = Offset; // ARM doesn't need the general 64-bit offsets
|
|
|
|
unsigned i = 0;
|
|
|
|
|
|
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
|
|
|
"This resolveFrameIndex does not support Thumb1!");
|
|
|
|
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
|
|
++i;
|
|
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
bool Done = false;
|
|
|
|
if (!AFI->isThumbFunction())
|
|
|
|
Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
|
|
|
|
else {
|
|
|
|
assert(AFI->isThumb2Function());
|
|
|
|
Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
|
|
|
|
}
|
|
|
|
assert (Done && "Unable to resolve frame index!");
|
2011-08-12 16:54:45 +02:00
|
|
|
(void)Done;
|
2010-08-18 00:41:55 +02:00
|
|
|
}
|
2010-08-17 20:13:53 +02:00
|
|
|
|
2010-08-20 01:52:25 +02:00
|
|
|
bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
|
|
|
|
int64_t Offset) const {
|
2011-06-28 21:10:37 +02:00
|
|
|
const MCInstrDesc &Desc = MI->getDesc();
|
2010-08-19 00:44:49 +02:00
|
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
|
|
unsigned i = 0;
|
|
|
|
|
|
|
|
while (!MI->getOperand(i).isFI()) {
|
|
|
|
++i;
|
|
|
|
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
|
|
|
|
}
|
|
|
|
|
|
|
|
// AddrMode4 and AddrMode6 cannot handle any offset.
|
|
|
|
if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
|
|
|
|
return Offset == 0;
|
|
|
|
|
|
|
|
unsigned NumBits = 0;
|
|
|
|
unsigned Scale = 1;
|
2010-08-20 01:52:25 +02:00
|
|
|
bool isSigned = true;
|
2010-08-26 23:56:30 +02:00
|
|
|
switch (AddrMode) {
|
2010-08-19 00:44:49 +02:00
|
|
|
case ARMII::AddrModeT2_i8:
|
|
|
|
case ARMII::AddrModeT2_i12:
|
|
|
|
// i8 supports only negative, and i12 supports only positive, so
|
|
|
|
// based on Offset sign, consider the appropriate instruction
|
2010-08-19 19:52:13 +02:00
|
|
|
Scale = 1;
|
2010-08-19 00:44:49 +02:00
|
|
|
if (Offset < 0) {
|
|
|
|
NumBits = 8;
|
|
|
|
Offset = -Offset;
|
|
|
|
} else {
|
|
|
|
NumBits = 12;
|
|
|
|
}
|
|
|
|
break;
|
2010-08-26 23:56:30 +02:00
|
|
|
case ARMII::AddrMode5:
|
2010-08-19 00:44:49 +02:00
|
|
|
// VFP address mode.
|
|
|
|
NumBits = 8;
|
|
|
|
Scale = 4;
|
|
|
|
break;
|
2010-10-27 00:37:02 +02:00
|
|
|
case ARMII::AddrMode_i12:
|
2010-08-26 23:56:30 +02:00
|
|
|
case ARMII::AddrMode2:
|
2010-08-19 00:44:49 +02:00
|
|
|
NumBits = 12;
|
|
|
|
break;
|
2010-08-26 23:56:30 +02:00
|
|
|
case ARMII::AddrMode3:
|
2010-08-19 00:44:49 +02:00
|
|
|
NumBits = 8;
|
|
|
|
break;
|
2011-10-11 23:40:47 +02:00
|
|
|
case ARMII::AddrModeT1_s:
|
|
|
|
NumBits = 5;
|
2010-08-19 19:52:13 +02:00
|
|
|
Scale = 4;
|
2010-08-20 01:52:25 +02:00
|
|
|
isSigned = false;
|
2010-08-19 19:52:13 +02:00
|
|
|
break;
|
2010-08-19 00:44:49 +02:00
|
|
|
default:
|
|
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
|
|
}
|
|
|
|
|
2010-08-26 23:56:30 +02:00
|
|
|
Offset += getFrameIndexInstrOffset(MI, i);
|
2010-08-31 20:49:31 +02:00
|
|
|
// Make sure the offset is encodable for instructions that scale the
|
|
|
|
// immediate.
|
|
|
|
if ((Offset & (Scale-1)) != 0)
|
|
|
|
return false;
|
|
|
|
|
2010-08-20 01:52:25 +02:00
|
|
|
if (isSigned && Offset < 0)
|
2010-08-19 00:44:49 +02:00
|
|
|
Offset = -Offset;
|
|
|
|
|
|
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
|
|
if ((unsigned)Offset <= Mask * Scale)
|
|
|
|
return true;
|
2010-08-18 19:57:37 +02:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-08-27 01:32:16 +02:00
|
|
|
void
|
2009-07-28 07:48:47 +02:00
|
|
|
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2013-01-31 21:02:54 +01:00
|
|
|
int SPAdj, unsigned FIOperandNum,
|
|
|
|
RegScavenger *RS) const {
|
2009-07-24 02:16:18 +02:00
|
|
|
MachineInstr &MI = *II;
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2013-06-07 07:54:19 +02:00
|
|
|
const ARMBaseInstrInfo &TII =
|
2014-08-05 04:39:49 +02:00
|
|
|
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
|
2014-08-04 23:25:23 +02:00
|
|
|
const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>(
|
2014-08-05 04:39:49 +02:00
|
|
|
MF.getSubtarget().getFrameLowering());
|
2009-07-24 02:16:18 +02:00
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
2009-07-28 07:48:47 +02:00
|
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
2009-09-18 23:42:44 +02:00
|
|
|
"This eliminateFrameIndex does not support Thumb1!");
|
2013-01-31 21:02:54 +01:00
|
|
|
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
2009-11-22 21:05:32 +01:00
|
|
|
unsigned FrameReg;
|
2009-07-24 02:16:18 +02:00
|
|
|
|
2010-11-20 16:59:32 +01:00
|
|
|
int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
|
2009-07-24 02:16:18 +02:00
|
|
|
|
2012-02-28 02:15:01 +01:00
|
|
|
// PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
|
|
|
|
// call frame setup/destroy instructions have already been eliminated. That
|
|
|
|
// means the stack pointer cannot be used to access the emergency spill slot
|
|
|
|
// when !hasReservedCallFrame().
|
|
|
|
#ifndef NDEBUG
|
2013-03-23 00:32:27 +01:00
|
|
|
if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
|
2012-02-28 02:15:01 +01:00
|
|
|
assert(TFI->hasReservedCallFrame(MF) &&
|
|
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
|
|
"functions without a reserved call frame");
|
|
|
|
assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
|
|
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
|
|
"functions with variable sized frame objects");
|
|
|
|
}
|
|
|
|
#endif // NDEBUG
|
|
|
|
|
2013-06-16 22:34:15 +02:00
|
|
|
assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
|
2010-04-26 09:39:25 +02:00
|
|
|
|
2009-11-01 22:12:51 +01:00
|
|
|
// Modify MI as necessary to handle as much of 'Offset' as possible
|
2009-08-27 03:23:50 +02:00
|
|
|
bool Done = false;
|
2009-07-28 07:48:47 +02:00
|
|
|
if (!AFI->isThumbFunction())
|
2013-01-31 21:02:54 +01:00
|
|
|
Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
|
2009-07-28 07:48:47 +02:00
|
|
|
else {
|
|
|
|
assert(AFI->isThumb2Function());
|
2013-01-31 21:02:54 +01:00
|
|
|
Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
|
2009-07-28 07:48:47 +02:00
|
|
|
}
|
2009-08-27 03:23:50 +02:00
|
|
|
if (Done)
|
2010-08-27 01:32:16 +02:00
|
|
|
return;
|
2009-07-24 02:16:18 +02:00
|
|
|
|
2009-07-08 20:31:39 +02:00
|
|
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
|
|
// as much as possible above, handle the rest, providing a register that is
|
|
|
|
// SP+LargeImm.
|
2009-08-28 10:08:22 +02:00
|
|
|
assert((Offset ||
|
2009-11-15 22:45:34 +01:00
|
|
|
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
|
|
|
|
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
|
2009-08-27 03:23:50 +02:00
|
|
|
"This code isn't needed if offset already handled!");
|
2009-07-08 20:31:39 +02:00
|
|
|
|
2009-10-20 03:26:58 +02:00
|
|
|
unsigned ScratchReg = 0;
|
2009-07-08 20:31:39 +02:00
|
|
|
int PIdx = MI.findFirstPredOperandIdx();
|
|
|
|
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
|
|
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
|
|
|
|
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
|
2009-08-27 03:23:50 +02:00
|
|
|
if (Offset == 0)
|
2009-11-15 22:45:34 +01:00
|
|
|
// Must be addrmode4/6.
|
2013-01-31 21:02:54 +01:00
|
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
|
2009-07-28 07:48:47 +02:00
|
|
|
else {
|
2012-04-20 09:30:17 +02:00
|
|
|
ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
|
2009-08-27 03:23:50 +02:00
|
|
|
if (!AFI->isThumbFunction())
|
|
|
|
emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
|
|
|
Offset, Pred, PredReg, TII);
|
|
|
|
else {
|
|
|
|
assert(AFI->isThumb2Function());
|
|
|
|
emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
|
|
|
Offset, Pred, PredReg, TII);
|
|
|
|
}
|
2010-12-09 02:22:13 +01:00
|
|
|
// Update the original instruction to use the scratch register.
|
2013-01-31 21:02:54 +01:00
|
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
|
2009-07-28 07:48:47 +02:00
|
|
|
}
|
2009-07-08 20:31:39 +02:00
|
|
|
}
|
2014-07-16 22:13:31 +02:00
|
|
|
|
|
|
|
bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
|
|
|
|
const TargetRegisterClass *SrcRC,
|
|
|
|
unsigned SubReg,
|
|
|
|
const TargetRegisterClass *DstRC,
|
|
|
|
unsigned DstSubReg,
|
|
|
|
const TargetRegisterClass *NewRC) const {
|
|
|
|
auto MBB = MI->getParent();
|
|
|
|
auto MF = MBB->getParent();
|
|
|
|
const MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
|
|
// If not copying into a sub-register this should be ok because we shouldn't
|
|
|
|
// need to split the reg.
|
|
|
|
if (!DstSubReg)
|
|
|
|
return true;
|
|
|
|
// Small registers don't frequently cause a problem, so we can coalesce them.
|
|
|
|
if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
auto NewRCWeight =
|
|
|
|
MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
|
|
|
|
auto SrcRCWeight =
|
|
|
|
MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
|
|
|
|
auto DstRCWeight =
|
|
|
|
MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
|
|
|
|
// If the source register class is more expensive than the destination, the
|
|
|
|
// coalescing is probably profitable.
|
|
|
|
if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
|
|
|
|
return true;
|
|
|
|
if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// If the register allocator isn't constrained, we can always allow coalescing
|
|
|
|
// unfortunately we don't know yet if we will be constrained.
|
|
|
|
// The goal of this heuristic is to restrict how many expensive registers
|
|
|
|
// we allow to coalesce in a given basic block.
|
|
|
|
auto AFI = MF->getInfo<ARMFunctionInfo>();
|
|
|
|
auto It = AFI->getCoalescedWeight(MBB);
|
|
|
|
|
|
|
|
DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
|
|
|
|
<< It->second << "\n");
|
|
|
|
DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
|
|
|
|
<< NewRCWeight.RegWeight << "\n");
|
|
|
|
|
|
|
|
// This number is the largest round number that which meets the criteria:
|
|
|
|
// (1) addresses PR18825
|
|
|
|
// (2) generates better code in some test cases (like vldm-shed-a9.ll)
|
|
|
|
// (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
|
|
|
|
// In practice the SizeMultiplier will only factor in for straight line code
|
|
|
|
// that uses a lot of NEON vectors, which isn't terribly common.
|
|
|
|
unsigned SizeMultiplier = MBB->size()/100;
|
|
|
|
SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
|
|
|
|
if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
|
|
|
|
It->second += NewRCWeight.RegWeight;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|