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llvm-mirror/test/CodeGen/X86/anyext.ll

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[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefix=X64
Don't use INSERT_SUBREG to model anyext operations on x86-64, as it leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. llvm-svn: 80099
2009-08-26 14:59:13 +00:00
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
2011-04-14 01:46:37 +00:00
; Use movzbl to avoid partial-register updates.
Don't use INSERT_SUBREG to model anyext operations on x86-64, as it leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. llvm-svn: 80099
2009-08-26 14:59:13 +00:00
define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X32-LABEL: foo:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 17:18:51 +00:00
; X32: # %bb.0:
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: divb {{[0-9]+}}(%esp)
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: andl $1, %eax
; X32-NEXT: retl
;
; X64-LABEL: foo:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 17:18:51 +00:00
; X64: # %bb.0:
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X64-NEXT: movzbl %dil, %eax
; X64-NEXT: divb %sil
; X64-NEXT: movzbl %al, %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
Don't use INSERT_SUBREG to model anyext operations on x86-64, as it leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. llvm-svn: 80099
2009-08-26 14:59:13 +00:00
%q = trunc i32 %p to i8
%r = udiv i8 %q, %x
%s = zext i8 %r to i32
%t = and i32 %s, 1
ret i32 %t
}
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
Don't use INSERT_SUBREG to model anyext operations on x86-64, as it leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. llvm-svn: 80099
2009-08-26 14:59:13 +00:00
define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X32-LABEL: bar:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 17:18:51 +00:00
; X32: # %bb.0:
[X86] Fix PR23155 by turning on X86FixupBWInsts by default. Differential Revision: http://reviews.llvm.org/D18866 llvm-svn: 265830
2016-04-08 18:58:29 +00:00
; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: divw {{[0-9]+}}(%esp)
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-01-31 22:04:26 +00:00
; X32-NEXT: # kill: def $ax killed $ax def $eax
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X32-NEXT: andl $1, %eax
; X32-NEXT: retl
;
; X64-LABEL: bar:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-04 17:18:51 +00:00
; X64: # %bb.0:
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr. This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
2016-05-07 01:11:17 +00:00
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-19 18:59:08 +00:00
; X64-NEXT: # kill: def $ax killed $ax killed $eax
Bias physical register immediate assignments The machine scheduler currently biases register copies to/from physical registers to be closer to their point of use / def to minimize their live ranges. This change extends this to also physical register assignments from immediate values. This causes a reduction in reduction in overall register pressure and minor reduction in spills and indirectly fixes an out-of-registers assertion (PR39391). Most test changes are from minor instruction reorderings and register name selection changes and direct consequences of that. Reviewers: MatzeB, qcolombet, myatsina, pcc Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya, javed.absar, arphaman, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D54218 llvm-svn: 346894
2018-11-14 21:11:53 +00:00
; X64-NEXT: xorl %edx, %edx
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X64-NEXT: divw %si
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-01-31 22:04:26 +00:00
; X64-NEXT: # kill: def $ax killed $ax def $eax
[X86] More thorough partial-register division checks For when grep counts are just not enough... llvm-svn: 260891
2016-02-15 14:09:35 +00:00
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
Don't use INSERT_SUBREG to model anyext operations on x86-64, as it leads to partial-register definitions. To help avoid redundant zero-extensions, also teach the h-register matching patterns that use movzbl to match anyext as well as zext. llvm-svn: 80099
2009-08-26 14:59:13 +00:00
%q = trunc i32 %p to i16
%r = udiv i16 %q, %x
%s = zext i16 %r to i32
%t = and i32 %s, 1
ret i32 %t
}
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