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llvm-mirror/test/CodeGen/PowerPC/and-mask.ll

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[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; mask 0xFFFFFFFE
define i32 @test1(i32 %a) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
[PowerPC] Exploit the rlwinm instructions for "and" with constant For now, PowerPC will using several instructions to get the constant and "and" it with the following case: define i32 @test1(i32 %a) { %and = and i32 %a, -2 ret i32 %and } However, we could exploit it with the rotate mask instructions. MB ME +----------------------+ |xxxxxxxxxxx00011111000| +----------------------+ 0 32 64 Notice that, we can only do it if the MB is larger than 32 and MB <= ME as RLWINM will replace the content of [0 - 32) with [32 - 64) even we didn't rotate it. Differential Revision: https://reviews.llvm.org/D71829
2019-12-30 03:18:31 +00:00
; CHECK-NEXT: rlwinm 3, 3, 0, 0, 30
[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; CHECK-NEXT: blr
%and = and i32 %a, -2
ret i32 %and
}
; mask 0xFFFFFFFFFFFFFFF9
define i64 @test2(i64 %a) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
[PowerPC] Exploit the rldicl + rldicl when and with mask If we are and the constant like 0xFFFFFFC00000, for now, we are using several instructions to generate this 48bit constant and final an "and". However, we could exploit it with two rotate instructions. MB ME MB+63-ME +----------------------+ +----------------------+ |0000001111111111111000| -> |0000000001111111111111| +----------------------+ +----------------------+ 0 63 0 63 Rotate left ME + 1 bit first, and then, mask it with (MB + 63 - ME, 63), finally, rotate back. Notice that, we need to round it with 64 bit for the wrapping case. Reviewed by: ChenZheng, Nemanjai Differential Revision: https://reviews.llvm.org/D71831
2020-04-17 05:24:00 +00:00
; CHECK-NEXT: rldicl 3, 3, 61, 2
; CHECK-NEXT: rotldi 3, 3, 3
[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; CHECK-NEXT: blr
%and = and i64 %a, -7
ret i64 %and
}
; mask: 0xFFFFFFC00000
define i64 @test3(i64 %a) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0:
[PowerPC] Exploit the rldicl + rldicl when and with mask If we are and the constant like 0xFFFFFFC00000, for now, we are using several instructions to generate this 48bit constant and final an "and". However, we could exploit it with two rotate instructions. MB ME MB+63-ME +----------------------+ +----------------------+ |0000001111111111111000| -> |0000000001111111111111| +----------------------+ +----------------------+ 0 63 0 63 Rotate left ME + 1 bit first, and then, mask it with (MB + 63 - ME, 63), finally, rotate back. Notice that, we need to round it with 64 bit for the wrapping case. Reviewed by: ChenZheng, Nemanjai Differential Revision: https://reviews.llvm.org/D71831
2020-04-17 05:24:00 +00:00
; CHECK-NEXT: rldicl 3, 3, 42, 22
; CHECK-NEXT: rldicl 3, 3, 22, 16
[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; CHECK-NEXT: blr
%and = and i64 %a, 281474972516352
ret i64 %and
}
; mask: 0xC000000FF
define i64 @test4(i64 %a) {
; CHECK-LABEL: test4:
; CHECK: # %bb.0:
[PowerPC] Exploit the rldicl + rldicl when and with mask If we are and the constant like 0xFFFFFFC00000, for now, we are using several instructions to generate this 48bit constant and final an "and". However, we could exploit it with two rotate instructions. MB ME MB+63-ME +----------------------+ +----------------------+ |0000001111111111111000| -> |0000000001111111111111| +----------------------+ +----------------------+ 0 63 0 63 Rotate left ME + 1 bit first, and then, mask it with (MB + 63 - ME, 63), finally, rotate back. Notice that, we need to round it with 64 bit for the wrapping case. Reviewed by: ChenZheng, Nemanjai Differential Revision: https://reviews.llvm.org/D71831
2020-04-17 05:24:00 +00:00
; CHECK-NEXT: rldicl 3, 3, 30, 26
; CHECK-NEXT: rldicl 3, 3, 34, 28
[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; CHECK-NEXT: blr
%and = and i64 %a, 51539607807
ret i64 %and
}
; mask: 0xFFC0FFFF
define i64 @test5(i64 %a) {
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
[PowerPC] Exploit the rldicl + rldicl when and with mask If we are and the constant like 0xFFFFFFC00000, for now, we are using several instructions to generate this 48bit constant and final an "and". However, we could exploit it with two rotate instructions. MB ME MB+63-ME +----------------------+ +----------------------+ |0000001111111111111000| -> |0000000001111111111111| +----------------------+ +----------------------+ 0 63 0 63 Rotate left ME + 1 bit first, and then, mask it with (MB + 63 - ME, 63), finally, rotate back. Notice that, we need to round it with 64 bit for the wrapping case. Reviewed by: ChenZheng, Nemanjai Differential Revision: https://reviews.llvm.org/D71831
2020-04-17 05:24:00 +00:00
; CHECK-NEXT: rldicl 3, 3, 42, 6
; CHECK-NEXT: rldicl 3, 3, 22, 32
[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; CHECK-NEXT: blr
%and = and i64 %a, 4290838527
ret i64 %and
}
; mask: 0x3FC0FFE0
define i64 @test6(i64 %a) {
; CHECK-LABEL: test6:
; CHECK: # %bb.0:
; CHECK-NEXT: lis 4, 16320
; CHECK-NEXT: ori 4, 4, 65504
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: blr
%and = and i64 %a, 1069613024
ret i64 %and
}
; mask: 0x3FC000001FFFF
define i64 @test7(i64 %a) {
; CHECK-LABEL: test7:
; CHECK: # %bb.0:
[PowerPC] Exploit the rldicl + rldicl when and with mask If we are and the constant like 0xFFFFFFC00000, for now, we are using several instructions to generate this 48bit constant and final an "and". However, we could exploit it with two rotate instructions. MB ME MB+63-ME +----------------------+ +----------------------+ |0000001111111111111000| -> |0000000001111111111111| +----------------------+ +----------------------+ 0 63 0 63 Rotate left ME + 1 bit first, and then, mask it with (MB + 63 - ME, 63), finally, rotate back. Notice that, we need to round it with 64 bit for the wrapping case. Reviewed by: ChenZheng, Nemanjai Differential Revision: https://reviews.llvm.org/D71831
2020-04-17 05:24:00 +00:00
; CHECK-NEXT: rldicl 3, 3, 22, 25
; CHECK-NEXT: rldicl 3, 3, 42, 14
[NFC][Test][PowerPC] Add more tests for 'and mask'
2019-12-23 06:59:14 +00:00
; CHECK-NEXT: blr
%and = and i64 %a, 1121501860462591
ret i64 %and
}
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