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llvm-mirror/test/CodeGen/X86/2008-10-27-CoalescerBug.ll

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Revert the test moves from 176733. Use "REQUIRES: asserts" instead. llvm-svn: 176873
2013-03-12 17:27:52 +01:00
; REQUIRES: asserts
Convert the uses of '|&' to use '2>&1 |' instead, which works on old versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. llvm-svn: 159544
2012-07-02 20:37:59 +02:00
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -stats 2>&1 | FileCheck %s
Re-enable register pressure aware machine licm with fixes. Hoist() may have erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
2010-10-19 20:58:51 +02:00
; Now this test spills one register. But a reload in the loop is cheaper than
; the divsd so it's a win.
Remove val# defined by a remat'ed def that is now dead. llvm-svn: 58294
2008-10-28 00:21:01 +01:00
define fastcc void @fourn(double* %data, i32 %isign) nounwind {
Re-enable register pressure aware machine licm with fixes. Hoist() may have erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
2010-10-19 20:58:51 +02:00
; CHECK: fourn
Remove val# defined by a remat'ed def that is now dead. llvm-svn: 58294
2008-10-28 00:21:01 +01:00
entry:
br label %bb
bb: ; preds = %bb, %entry
%indvar93 = phi i32 [ 0, %entry ], [ %idim.030, %bb ] ; <i32> [#uses=2]
%idim.030 = add i32 %indvar93, 1 ; <i32> [#uses=1]
%0 = add i32 %indvar93, 2 ; <i32> [#uses=1]
%1 = icmp sgt i32 %0, 2 ; <i1> [#uses=1]
br i1 %1, label %bb30.loopexit, label %bb
Re-enable register pressure aware machine licm with fixes. Hoist() may have erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. llvm-svn: 116845
2010-10-19 20:58:51 +02:00
; CHECK: %bb30.loopexit
; CHECK: divsd %xmm0
; CHECK: movsd %xmm0, 16(%esp)
Add a much more conservative strategy for aligning branch targets. Previously, MBP essentially aligned every branch target it could. This bloats code quite a bit, especially non-looping code which has no real reason to prefer aligned branch targets so heavily. As Andy said in review, it's still a bit odd to do this without a real cost model, but this at least has much more plausible heuristics. Fixes PR13265. llvm-svn: 161409
2012-08-07 11:45:24 +02:00
; CHECK: %bb3
Remove val# defined by a remat'ed def that is now dead. llvm-svn: 58294
2008-10-28 00:21:01 +01:00
bb3: ; preds = %bb30.loopexit, %bb25, %bb3
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-27 22:17:42 +01:00
%2 = load i32, i32* null, align 4 ; <i32> [#uses=1]
Remove val# defined by a remat'ed def that is now dead. llvm-svn: 58294
2008-10-28 00:21:01 +01:00
%3 = mul i32 %2, 0 ; <i32> [#uses=1]
%4 = icmp slt i32 0, %3 ; <i1> [#uses=1]
br i1 %4, label %bb18, label %bb3
bb18: ; preds = %bb3
%5 = fdiv double %11, 0.000000e+00 ; <double> [#uses=1]
%6 = tail call double @sin(double %5) nounwind readonly ; <double> [#uses=1]
br label %bb24.preheader
bb22.preheader: ; preds = %bb24.preheader, %bb22.preheader
br label %bb22.preheader
bb25: ; preds = %bb24.preheader
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 00:49:04 +02:00
%7 = fmul double 0.000000e+00, %6 ; <double> [#uses=0]
Remove val# defined by a remat'ed def that is now dead. llvm-svn: 58294
2008-10-28 00:21:01 +01:00
%8 = add i32 %i3.122100, 0 ; <i32> [#uses=1]
%9 = icmp sgt i32 %8, 0 ; <i1> [#uses=1]
br i1 %9, label %bb3, label %bb24.preheader
bb24.preheader: ; preds = %bb25, %bb18
%i3.122100 = or i32 0, 1 ; <i32> [#uses=2]
%10 = icmp slt i32 0, %i3.122100 ; <i1> [#uses=1]
br i1 %10, label %bb25, label %bb22.preheader
bb30.loopexit: ; preds = %bb
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 00:49:04 +02:00
%11 = fmul double 0.000000e+00, 0x401921FB54442D1C ; <double> [#uses=1]
Remove val# defined by a remat'ed def that is now dead. llvm-svn: 58294
2008-10-28 00:21:01 +01:00
br label %bb3
}
declare double @sin(double) nounwind readonly
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