2013-08-13 22:54:07 +02:00
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//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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2014-07-10 19:26:51 +02:00
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def HasMSA : Predicate<"Subtarget->hasMSA()">,
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2013-08-13 22:54:07 +02:00
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AssemblerPredicate<"FeatureMSA">;
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class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasMSA];
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let Inst{31-26} = 0b011110;
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}
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2014-01-29 15:05:28 +01:00
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class MSA64Inst : MSAInst {
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let Predicates = [HasMSA, HasMips64];
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}
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2013-10-22 11:43:32 +02:00
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class MSACBranch : MSAInst {
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let Inst{31-26} = 0b010001;
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}
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2013-10-23 15:20:07 +02:00
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class MSASpecial : MSAInst {
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let Inst{31-26} = 0b000000;
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}
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2014-02-10 13:05:17 +01:00
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class MSA64Special : MSA64Inst {
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let Inst{31-26} = 0b000000;
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}
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2013-11-20 15:32:28 +01:00
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class MSAPseudo<dag outs, dag ins, list<dag> pattern,
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2013-08-13 22:54:07 +02:00
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InstrItinClass itin = IIPseudo>:
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MipsPseudo<outs, ins, pattern, itin> {
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let Predicates = [HasMSA];
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}
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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bits<5> ws;
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bits<5> wd;
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bits<3> m;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{25-23} = major;
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let Inst{22-19} = 0b1110;
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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let Inst{18-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{5-0} = minor;
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}
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class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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bits<5> ws;
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bits<5> wd;
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bits<4> m;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{25-23} = major;
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let Inst{22-20} = 0b110;
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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let Inst{19-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{5-0} = minor;
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}
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class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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bits<5> ws;
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bits<5> wd;
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bits<5> m;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{25-23} = major;
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let Inst{22-21} = 0b10;
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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let Inst{20-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{5-0} = minor;
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}
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class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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bits<5> ws;
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bits<5> wd;
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bits<6> m;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{25-23} = major;
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let Inst{22} = 0b0;
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[mips][msa] Direct Object Emission support for BIT instructions.
List of instructions:
bclri.{b,h,w,d}
binsli.{b,h,w,d}
binsri.{b,h,w,d}
bnegi.{b,h,w,d}
bseti.{b,h,w,d}
sat_s.{b,h,w,d}
sat_u.{b,h,w,d}
slli.{b,h,w,d}
srai.{b,h,w,d}
srari.{b,h,w,d}
srli.{b,h,w,d}
srlri.{b,h,w,d}
llvm-svn: 192589
2013-10-14 15:07:39 +02:00
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let Inst{21-16} = m;
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{5-0} = minor;
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}
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2013-09-30 19:43:04 +02:00
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class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
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bits<5> rs;
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bits<5> wd;
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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2014-01-29 16:12:02 +01:00
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class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst {
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bits<5> rs;
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bits<5> wd;
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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let Inst{15-11} = rs;
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let Inst{10-6} = wd;
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let Inst{5-0} = minor;
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}
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
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2013-09-30 19:52:33 +02:00
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bits<5> ws;
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bits<5> wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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2013-09-30 19:52:33 +02:00
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{5-0} = minor;
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}
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class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
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2013-09-26 01:50:44 +02:00
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bits<5> ws;
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bits<5> wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
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let Inst{25-17} = major;
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let Inst{16} = df;
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2013-09-26 01:50:44 +02:00
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let Inst{15-11} = ws;
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let Inst{10-6} = wd;
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[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2013-08-13 22:54:07 +02:00
|
|
|
class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
|
2013-09-26 02:09:46 +02:00
|
|
|
bits<5> wt;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
2013-08-13 22:54:07 +02:00
|
|
|
let Inst{25-23} = major;
|
|
|
|
let Inst{22-21} = df;
|
2013-09-26 02:09:46 +02:00
|
|
|
let Inst{20-16} = wt;
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
2013-08-13 22:54:07 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
|
2013-09-26 23:31:43 +02:00
|
|
|
bits<5> wt;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21} = df;
|
2013-09-26 23:31:43 +02:00
|
|
|
let Inst{20-16} = wt;
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2013-10-21 13:47:56 +02:00
|
|
|
class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
|
|
|
|
bits<5> rt;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
|
|
|
let Inst{25-23} = major;
|
|
|
|
let Inst{22-21} = df;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2013-08-28 12:26:24 +02:00
|
|
|
class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
|
2013-10-21 14:43:54 +02:00
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
2013-08-28 12:26:24 +02:00
|
|
|
let Inst{25-16} = major;
|
2013-10-21 14:43:54 +02:00
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
2013-08-28 12:26:24 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2013-10-21 14:26:50 +02:00
|
|
|
class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<5> rd;
|
|
|
|
bits<5> cs;
|
|
|
|
|
|
|
|
let Inst{25-16} = major;
|
|
|
|
let Inst{15-11} = cs;
|
|
|
|
let Inst{10-6} = rd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> cd;
|
|
|
|
|
|
|
|
let Inst{25-16} = major;
|
|
|
|
let Inst{15-11} = rs;
|
|
|
|
let Inst{10-6} = cd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-20} = 0b00;
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
let Inst{19-16} = n{3-0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-19} = 0b100;
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
let Inst{18-16} = n{2-0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-18} = 0b1100;
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
let Inst{17-16} = n{1-0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-17} = 0b11100;
|
[mips][msa] Direct Object Emission for the majority of the ELM instructions.
List of instructions:
copy_s.{b,h,w}
copy_u.{b,h,w}
sldi.{b,h,w,d}
splati.{b,h,w,d}
llvm-svn: 192586
2013-10-14 14:22:43 +02:00
|
|
|
let Inst{16} = n{0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-20} = 0b00;
|
|
|
|
let Inst{19-16} = n{3-0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = rd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-19} = 0b100;
|
|
|
|
let Inst{18-16} = n{2-0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = rd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-18} = 0b1100;
|
|
|
|
let Inst{17-16} = n{1-0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = rd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2014-01-29 15:05:28 +01:00
|
|
|
class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
|
|
|
|
bits<4> n;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> rd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-17} = 0b11100;
|
|
|
|
let Inst{16} = n{0};
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = rd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2013-10-14 13:49:30 +02:00
|
|
|
class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<6> n;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> wd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-20} = 0b00;
|
|
|
|
let Inst{19-16} = n{3-0};
|
|
|
|
let Inst{15-11} = rs;
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<6> n;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> wd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-19} = 0b100;
|
|
|
|
let Inst{18-16} = n{2-0};
|
|
|
|
let Inst{15-11} = rs;
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
|
|
|
|
bits<6> n;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> wd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-18} = 0b1100;
|
|
|
|
let Inst{17-16} = n{1-0};
|
|
|
|
let Inst{15-11} = rs;
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2014-01-31 14:31:20 +01:00
|
|
|
class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSA64Inst {
|
|
|
|
bits<6> n;
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> wd;
|
|
|
|
|
|
|
|
let Inst{25-22} = major;
|
|
|
|
let Inst{21-17} = 0b11100;
|
|
|
|
let Inst{16} = n{0};
|
|
|
|
let Inst{15-11} = rs;
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
2013-08-13 22:54:07 +02:00
|
|
|
class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
|
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
llvm-svn: 191687
2013-09-30 19:58:07 +02:00
|
|
|
bits<5> imm;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
2013-08-13 22:54:07 +02:00
|
|
|
let Inst{25-23} = major;
|
|
|
|
let Inst{22-21} = df;
|
[mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
llvm-svn: 191687
2013-09-30 19:58:07 +02:00
|
|
|
let Inst{20-16} = imm;
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
2013-08-13 22:54:07 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
|
|
|
|
class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
|
2013-09-30 20:05:18 +02:00
|
|
|
bits<8> u8;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-24} = major;
|
2013-09-30 20:05:18 +02:00
|
|
|
let Inst{23-16} = u8;
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
|
2013-10-21 14:56:20 +02:00
|
|
|
bits<10> s10;
|
|
|
|
bits<5> wd;
|
|
|
|
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{25-23} = major;
|
|
|
|
let Inst{22-21} = df;
|
2013-10-21 14:56:20 +02:00
|
|
|
let Inst{20-11} = s10;
|
|
|
|
let Inst{10-6} = wd;
|
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi
Patch by Daniel Sanders
llvm-svn: 188457
2013-08-15 14:24:57 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
2013-08-20 10:38:21 +02:00
|
|
|
|
2013-10-21 15:07:13 +02:00
|
|
|
class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst {
|
|
|
|
bits<21> addr;
|
|
|
|
bits<5> wd;
|
|
|
|
|
|
|
|
let Inst{25-16} = addr{9-0};
|
|
|
|
let Inst{15-11} = addr{20-16};
|
|
|
|
let Inst{10-6} = wd;
|
|
|
|
let Inst{5-2} = minor;
|
|
|
|
let Inst{1-0} = df;
|
|
|
|
}
|
|
|
|
|
2013-08-20 10:38:21 +02:00
|
|
|
class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
|
2013-10-14 14:57:18 +02:00
|
|
|
bits<5> wt;
|
|
|
|
bits<5> ws;
|
|
|
|
bits<5> wd;
|
|
|
|
|
2013-08-20 10:38:21 +02:00
|
|
|
let Inst{25-21} = major;
|
2013-10-14 14:57:18 +02:00
|
|
|
let Inst{20-16} = wt;
|
|
|
|
let Inst{15-11} = ws;
|
|
|
|
let Inst{10-6} = wd;
|
2013-08-20 10:38:21 +02:00
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|
2013-08-28 14:14:50 +02:00
|
|
|
|
2013-10-22 11:43:32 +02:00
|
|
|
class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch {
|
|
|
|
bits<16> offset;
|
|
|
|
bits<5> wt;
|
|
|
|
|
|
|
|
let Inst{25-23} = major;
|
|
|
|
let Inst{22-21} = df;
|
|
|
|
let Inst{20-16} = wt;
|
|
|
|
let Inst{15-0} = offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch {
|
|
|
|
bits<16> offset;
|
|
|
|
bits<5> wt;
|
|
|
|
|
2013-08-28 14:14:50 +02:00
|
|
|
let Inst{25-21} = major;
|
2013-10-22 11:43:32 +02:00
|
|
|
let Inst{20-16} = wt;
|
|
|
|
let Inst{15-0} = offset;
|
2013-08-28 14:14:50 +02:00
|
|
|
}
|
2013-10-17 15:38:20 +02:00
|
|
|
|
2013-10-23 15:20:07 +02:00
|
|
|
class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
bits<5> rd;
|
|
|
|
bits<2> sa;
|
|
|
|
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = rd;
|
2013-10-17 15:38:20 +02:00
|
|
|
let Inst{10-8} = 0b000;
|
2013-10-23 15:20:07 +02:00
|
|
|
let Inst{7-6} = sa;
|
|
|
|
let Inst{5-0} = minor;
|
2013-10-17 15:38:20 +02:00
|
|
|
}
|
2014-02-10 13:05:17 +01:00
|
|
|
|
|
|
|
class SPECIAL_DLSA_FMT<bits<6> minor>: MSA64Special {
|
|
|
|
bits<5> rs;
|
|
|
|
bits<5> rt;
|
|
|
|
bits<5> rd;
|
|
|
|
bits<2> sa;
|
|
|
|
|
|
|
|
let Inst{25-21} = rs;
|
|
|
|
let Inst{20-16} = rt;
|
|
|
|
let Inst{15-11} = rd;
|
|
|
|
let Inst{10-8} = 0b000;
|
|
|
|
let Inst{7-6} = sa;
|
|
|
|
let Inst{5-0} = minor;
|
|
|
|
}
|