2016-11-11 09:27:37 +01:00
|
|
|
//===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
|
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// \file
|
|
|
|
/// This file implements the targeting of the RegisterBankInfo class for ARM.
|
|
|
|
/// \todo This should be generated by TableGen.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "ARMRegisterBankInfo.h"
|
2016-12-16 13:54:46 +01:00
|
|
|
#include "ARMInstrInfo.h" // For the register classes
|
2017-02-16 12:25:09 +01:00
|
|
|
#include "ARMSubtarget.h"
|
2016-11-11 09:27:37 +01:00
|
|
|
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
|
|
|
|
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
|
|
#include "llvm/Target/TargetRegisterInfo.h"
|
|
|
|
|
2017-02-05 13:07:55 +01:00
|
|
|
#define GET_TARGET_REGBANK_IMPL
|
|
|
|
#include "ARMGenRegisterBank.inc"
|
|
|
|
|
2016-11-11 09:27:37 +01:00
|
|
|
using namespace llvm;
|
|
|
|
|
|
|
|
#ifndef LLVM_BUILD_GLOBAL_ISEL
|
|
|
|
#error "You shouldn't build this"
|
|
|
|
#endif
|
|
|
|
|
2016-12-16 13:54:46 +01:00
|
|
|
// FIXME: TableGen this.
|
|
|
|
// If it grows too much and TableGen still isn't ready to do the job, extract it
|
|
|
|
// into an ARMGenRegisterBankInfo.def (similar to AArch64).
|
|
|
|
namespace llvm {
|
|
|
|
namespace ARM {
|
2017-02-17 14:14:25 +01:00
|
|
|
enum PartialMappingIdx {
|
|
|
|
PMI_GPR,
|
|
|
|
PMI_SPR,
|
|
|
|
PMI_DPR,
|
|
|
|
PMI_Min = PMI_GPR,
|
|
|
|
};
|
|
|
|
|
|
|
|
RegisterBankInfo::PartialMapping PartMappings[]{
|
|
|
|
// GPR Partial Mapping
|
|
|
|
{0, 32, GPRRegBank},
|
|
|
|
// SPR Partial Mapping
|
|
|
|
{0, 32, FPRRegBank},
|
|
|
|
// DPR Partial Mapping
|
|
|
|
{0, 64, FPRRegBank},
|
|
|
|
};
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM,
|
|
|
|
unsigned Start, unsigned Length,
|
|
|
|
unsigned RegBankID) {
|
|
|
|
return PM.StartIdx == Start && PM.Length == Length &&
|
|
|
|
PM.RegBank->getID() == RegBankID;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void checkPartialMappings() {
|
|
|
|
assert(
|
|
|
|
checkPartMapping(PartMappings[PMI_GPR - PMI_Min], 0, 32, GPRRegBankID) &&
|
|
|
|
"Wrong mapping for GPR");
|
|
|
|
assert(
|
|
|
|
checkPartMapping(PartMappings[PMI_SPR - PMI_Min], 0, 32, FPRRegBankID) &&
|
|
|
|
"Wrong mapping for SPR");
|
|
|
|
assert(
|
|
|
|
checkPartMapping(PartMappings[PMI_DPR - PMI_Min], 0, 64, FPRRegBankID) &&
|
|
|
|
"Wrong mapping for DPR");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
enum ValueMappingIdx {
|
|
|
|
InvalidIdx = 0,
|
|
|
|
GPR3OpsIdx = 1,
|
|
|
|
SPR3OpsIdx = 4,
|
|
|
|
DPR3OpsIdx = 7,
|
|
|
|
};
|
2016-12-16 13:54:46 +01:00
|
|
|
|
|
|
|
RegisterBankInfo::ValueMapping ValueMappings[] = {
|
2017-02-17 14:14:25 +01:00
|
|
|
// invalid
|
|
|
|
{nullptr, 0},
|
|
|
|
// 3 ops in GPRs
|
|
|
|
{&PartMappings[PMI_GPR - PMI_Min], 1},
|
|
|
|
{&PartMappings[PMI_GPR - PMI_Min], 1},
|
|
|
|
{&PartMappings[PMI_GPR - PMI_Min], 1},
|
|
|
|
// 3 ops in SPRs
|
|
|
|
{&PartMappings[PMI_SPR - PMI_Min], 1},
|
|
|
|
{&PartMappings[PMI_SPR - PMI_Min], 1},
|
|
|
|
{&PartMappings[PMI_SPR - PMI_Min], 1},
|
|
|
|
// 3 ops in DPRs
|
|
|
|
{&PartMappings[PMI_DPR - PMI_Min], 1},
|
|
|
|
{&PartMappings[PMI_DPR - PMI_Min], 1},
|
|
|
|
{&PartMappings[PMI_DPR - PMI_Min], 1}};
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM,
|
|
|
|
RegisterBankInfo::PartialMapping *BreakDown) {
|
|
|
|
return VM.NumBreakDowns == 1 && VM.BreakDown == BreakDown;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void checkValueMappings() {
|
|
|
|
assert(checkValueMapping(ValueMappings[GPR3OpsIdx],
|
|
|
|
&PartMappings[PMI_GPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 GPR ops instruction");
|
|
|
|
assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 1],
|
|
|
|
&PartMappings[PMI_GPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 GPR ops instruction");
|
|
|
|
assert(checkValueMapping(ValueMappings[GPR3OpsIdx + 2],
|
|
|
|
&PartMappings[PMI_GPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 GPR ops instruction");
|
|
|
|
|
|
|
|
assert(checkValueMapping(ValueMappings[SPR3OpsIdx],
|
|
|
|
&PartMappings[PMI_SPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 SPR ops instruction");
|
|
|
|
assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 1],
|
|
|
|
&PartMappings[PMI_SPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 SPR ops instruction");
|
|
|
|
assert(checkValueMapping(ValueMappings[SPR3OpsIdx + 2],
|
|
|
|
&PartMappings[PMI_SPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 SPR ops instruction");
|
|
|
|
|
|
|
|
assert(checkValueMapping(ValueMappings[DPR3OpsIdx],
|
|
|
|
&PartMappings[PMI_DPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 DPR ops instruction");
|
|
|
|
assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 1],
|
|
|
|
&PartMappings[PMI_DPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 DPR ops instruction");
|
|
|
|
assert(checkValueMapping(ValueMappings[DPR3OpsIdx + 2],
|
|
|
|
&PartMappings[PMI_DPR - PMI_Min]) &&
|
|
|
|
"Wrong value mapping for 3 DPR ops instruction");
|
|
|
|
}
|
|
|
|
#endif
|
2016-12-16 13:54:46 +01:00
|
|
|
} // end namespace arm
|
|
|
|
} // end namespace llvm
|
|
|
|
|
2016-11-11 09:27:37 +01:00
|
|
|
ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
|
2017-02-05 13:07:55 +01:00
|
|
|
: ARMGenRegisterBankInfo() {
|
2016-12-16 13:54:46 +01:00
|
|
|
static bool AlreadyInit = false;
|
|
|
|
// We have only one set of register banks, whatever the subtarget
|
|
|
|
// is. Therefore, the initialization of the RegBanks table should be
|
|
|
|
// done only once. Indeed the table of all register banks
|
|
|
|
// (ARM::RegBanks) is unique in the compiler. At some point, it
|
|
|
|
// will get tablegen'ed and the whole constructor becomes empty.
|
|
|
|
if (AlreadyInit)
|
|
|
|
return;
|
|
|
|
AlreadyInit = true;
|
|
|
|
|
|
|
|
const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
|
|
|
|
(void)RBGPR;
|
|
|
|
assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
|
2017-01-12 17:11:23 +01:00
|
|
|
|
|
|
|
// Initialize the GPR bank.
|
2016-12-16 13:54:46 +01:00
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
|
|
|
|
"Subclass not added?");
|
|
|
|
assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
|
2017-02-17 14:14:25 +01:00
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
ARM::checkPartialMappings();
|
|
|
|
ARM::checkValueMappings();
|
|
|
|
#endif
|
2016-12-16 13:54:46 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
|
|
|
|
const TargetRegisterClass &RC) const {
|
|
|
|
using namespace ARM;
|
|
|
|
|
|
|
|
switch (RC.getID()) {
|
|
|
|
case GPRRegClassID:
|
2017-01-25 09:10:40 +01:00
|
|
|
case GPRnopcRegClassID:
|
2017-03-13 15:28:34 +01:00
|
|
|
case GPRspRegClassID:
|
2016-12-16 13:54:46 +01:00
|
|
|
case tGPR_and_tcGPRRegClassID:
|
2017-02-24 14:07:25 +01:00
|
|
|
case tGPRRegClassID:
|
2016-12-16 13:54:46 +01:00
|
|
|
return getRegBank(ARM::GPRRegBankID);
|
2017-02-08 14:23:04 +01:00
|
|
|
case SPR_8RegClassID:
|
|
|
|
case SPRRegClassID:
|
2017-02-16 11:12:49 +01:00
|
|
|
case DPR_8RegClassID:
|
|
|
|
case DPRRegClassID:
|
2017-02-08 14:23:04 +01:00
|
|
|
return getRegBank(ARM::FPRRegBankID);
|
2016-12-16 13:54:46 +01:00
|
|
|
default:
|
|
|
|
llvm_unreachable("Unsupported register kind");
|
|
|
|
}
|
|
|
|
|
|
|
|
llvm_unreachable("Switch should handle all register classes");
|
|
|
|
}
|
|
|
|
|
2017-05-06 00:48:22 +02:00
|
|
|
const RegisterBankInfo::InstructionMapping &
|
2016-12-16 13:54:46 +01:00
|
|
|
ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
|
|
|
auto Opc = MI.getOpcode();
|
|
|
|
|
|
|
|
// Try the default logic for non-generic instructions that are either copies
|
|
|
|
// or already have some operands assigned to banks.
|
|
|
|
if (!isPreISelGenericOpcode(Opc)) {
|
2017-05-06 00:48:22 +02:00
|
|
|
const InstructionMapping &Mapping = getInstrMappingImpl(MI);
|
2016-12-16 13:54:46 +01:00
|
|
|
if (Mapping.isValid())
|
|
|
|
return Mapping;
|
|
|
|
}
|
|
|
|
|
2016-12-19 12:26:31 +01:00
|
|
|
using namespace TargetOpcode;
|
|
|
|
|
2017-02-16 11:12:49 +01:00
|
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
|
|
|
|
|
2016-12-19 12:26:31 +01:00
|
|
|
unsigned NumOperands = MI.getNumOperands();
|
2017-02-17 14:14:25 +01:00
|
|
|
const ValueMapping *OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
|
2016-12-19 12:26:31 +01:00
|
|
|
|
|
|
|
switch (Opc) {
|
|
|
|
case G_ADD:
|
2017-04-18 14:35:28 +02:00
|
|
|
case G_SUB:
|
2017-04-19 09:29:46 +02:00
|
|
|
case G_MUL:
|
2017-06-07 11:17:41 +02:00
|
|
|
case G_AND:
|
2017-06-07 12:14:23 +02:00
|
|
|
case G_OR:
|
2017-06-07 13:57:30 +02:00
|
|
|
case G_XOR:
|
2017-04-24 10:20:05 +02:00
|
|
|
case G_SDIV:
|
|
|
|
case G_UDIV:
|
2017-01-25 09:10:40 +01:00
|
|
|
case G_SEXT:
|
|
|
|
case G_ZEXT:
|
2017-05-11 10:28:31 +02:00
|
|
|
case G_ANYEXT:
|
2017-04-21 15:16:50 +02:00
|
|
|
case G_TRUNC:
|
2017-02-28 10:35:10 +01:00
|
|
|
case G_GEP:
|
2016-12-19 12:26:31 +01:00
|
|
|
// FIXME: We're abusing the fact that everything lives in a GPR for now; in
|
|
|
|
// the real world we would use different mappings.
|
2017-02-17 14:14:25 +01:00
|
|
|
OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx];
|
2016-12-19 12:26:31 +01:00
|
|
|
break;
|
2017-02-16 11:12:49 +01:00
|
|
|
case G_LOAD:
|
2017-02-24 14:07:25 +01:00
|
|
|
case G_STORE:
|
2017-02-17 14:14:25 +01:00
|
|
|
OperandsMapping =
|
|
|
|
Ty.getSizeInBits() == 64
|
|
|
|
? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
|
|
|
|
&ARM::ValueMappings[ARM::GPR3OpsIdx]})
|
|
|
|
: &ARM::ValueMappings[ARM::GPR3OpsIdx];
|
2017-02-16 11:12:49 +01:00
|
|
|
break;
|
2017-02-08 14:23:04 +01:00
|
|
|
case G_FADD:
|
2017-02-16 11:12:49 +01:00
|
|
|
assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) &&
|
|
|
|
"Unsupported size for G_FADD");
|
2017-02-17 14:14:25 +01:00
|
|
|
OperandsMapping = Ty.getSizeInBits() == 64
|
|
|
|
? &ARM::ValueMappings[ARM::DPR3OpsIdx]
|
|
|
|
: &ARM::ValueMappings[ARM::SPR3OpsIdx];
|
2017-02-08 14:23:04 +01:00
|
|
|
break;
|
2017-02-28 13:13:58 +01:00
|
|
|
case G_CONSTANT:
|
2016-12-19 12:26:31 +01:00
|
|
|
case G_FRAME_INDEX:
|
2017-02-17 14:14:25 +01:00
|
|
|
OperandsMapping =
|
|
|
|
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr});
|
2016-12-19 12:26:31 +01:00
|
|
|
break;
|
2017-06-07 14:35:05 +02:00
|
|
|
case G_MERGE_VALUES: {
|
|
|
|
// We only support G_MERGE_VALUES for creating a double precision floating
|
|
|
|
// point value out of two GPRs.
|
2017-02-16 12:00:31 +01:00
|
|
|
LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
|
2017-06-07 14:35:05 +02:00
|
|
|
LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
|
2017-02-16 12:00:31 +01:00
|
|
|
if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
|
|
|
|
Ty2.getSizeInBits() != 32)
|
2017-05-06 00:48:22 +02:00
|
|
|
return getInvalidInstructionMapping();
|
2017-02-16 12:00:31 +01:00
|
|
|
OperandsMapping =
|
2017-02-17 14:14:25 +01:00
|
|
|
getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
|
2017-06-07 14:35:05 +02:00
|
|
|
&ARM::ValueMappings[ARM::GPR3OpsIdx],
|
|
|
|
&ARM::ValueMappings[ARM::GPR3OpsIdx]});
|
2017-02-16 12:00:31 +01:00
|
|
|
break;
|
|
|
|
}
|
2017-06-07 14:35:05 +02:00
|
|
|
case G_UNMERGE_VALUES: {
|
|
|
|
// We only support G_UNMERGE_VALUES for splitting a double precision
|
|
|
|
// floating point value into two GPRs.
|
2017-02-16 12:00:31 +01:00
|
|
|
LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
|
2017-06-07 14:35:05 +02:00
|
|
|
LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
|
|
|
|
if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
|
|
|
|
Ty2.getSizeInBits() != 64)
|
2017-05-06 00:48:22 +02:00
|
|
|
return getInvalidInstructionMapping();
|
2017-06-07 14:35:05 +02:00
|
|
|
OperandsMapping =
|
|
|
|
getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
|
|
|
|
&ARM::ValueMappings[ARM::GPR3OpsIdx],
|
|
|
|
&ARM::ValueMappings[ARM::DPR3OpsIdx]});
|
2017-02-16 12:00:31 +01:00
|
|
|
break;
|
|
|
|
}
|
2016-12-19 12:26:31 +01:00
|
|
|
default:
|
2017-05-06 00:48:22 +02:00
|
|
|
return getInvalidInstructionMapping();
|
2016-12-16 13:54:46 +01:00
|
|
|
}
|
|
|
|
|
2017-02-16 12:25:09 +01:00
|
|
|
#ifndef NDEBUG
|
|
|
|
for (unsigned i = 0; i < NumOperands; i++) {
|
|
|
|
for (const auto &Mapping : OperandsMapping[i]) {
|
|
|
|
assert(
|
|
|
|
(Mapping.RegBank->getID() != ARM::FPRRegBankID ||
|
|
|
|
MF.getSubtarget<ARMSubtarget>().hasVFP2()) &&
|
|
|
|
"Trying to use floating point register bank on target without vfp");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-05-06 00:48:22 +02:00
|
|
|
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
|
|
|
|
NumOperands);
|
2016-12-16 13:54:46 +01:00
|
|
|
}
|