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llvm-mirror/test/MC/Disassembler/thumb-tests.txt

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Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s
# CHECK: add r5, sp, #68
0x11 0xad
# CHECK: adcs r0, r0, #1
0x50 0xf1 0x01 0x00
# CHECK: b #34
0x0f 0xe0
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1 Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. llvm-svn: 101817
2010-04-19 23:19:52 +02:00
# CHECK: b.w #-12
0xff 0xf7 0xf8 0xaf
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: bfi r2, r10, #0, #1
0x6a 0xf3 0x00 0x02
# CHECK: cbnz r7, #20
0x57 0xb9
# CHECK: cmp r3, r4
0xa3 0x42
# CHECK: cmn.w r0, #31
0x10 0xf1 0x1f 0x0f
# CHECK: ldmia r0!, {r1}
0x02 0xc8
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT llvm-svn: 101915
2010-04-20 19:28:50 +02:00
# CHECK: ldrb.w r8, #-24
0x1f 0xf8 0x18 0x80
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: ldrd r0, r1, [r7, #64]!
0xf7 0xe9 0x10 0x01
# CHECK: lsls.w r0, pc, #1
0x5f 0xea 0x4f 0x00
# CHECK: mov r11, r7
0xbb 0x46
# CHECK: pkhtb r2, r4, r6, asr #16
0xc4 0xea 0x26 0x42
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
2010-08-17 19:23:19 +02:00
# CHECK-NOT: pkhbt r2, r4, r6, lsl #0
# CHECK: pkhbt r2, r4, r6
0xc4 0xea 0x06 0x02
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: pop {r2, r4, r6, r8, r10, r12}
0xbd 0xe8 0x54 0x15
# CHECK: push {r2, r4, r6, r8, r10, r12}
0x2d 0xe9 0x54 0x15
# CHECK: rsbs r0, r0, #0
0x40 0x42
Add a Thumb2 t2RSBrr instruction for disassembly only. This fixes another part of PR7792. llvm-svn: 111057
2010-08-14 01:24:25 +02:00
# CHECK-NOT: rsb r0, r2, r0, lsl #0
# CHECK: rsb r0, r2, r0
0xc2 0xeb 0x00 0x00
Move the Thumb2 SSAT and USAT optional shift operator out of the instruction opcode. This fixes part of PR7792. llvm-svn: 111047
2010-08-13 23:48:10 +02:00
# CHECK-NOT: ssat r0, #17, r12, lsl #0
# CHECK: ssat r0, #17, r12
0x0c 0xf3 0x10 0x00
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: strd r0, [r7, #64]
0xc7 0xe9 0x10 0x01
# CHECK: sub sp, #60
0x8f 0xb0
# CHECK: subw r0, pc, #1
0xaf 0xf2 0x01 0x00
When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. llvm-svn: 101929
2010-04-20 20:45:24 +02:00
# CHECK: subw r0, sp, #835
0xad 0xf2 0x43 0x30
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: uqadd16 r3, r4, r5
0x94 0xfa 0x55 0xf3
# CHECK: usada8 r5, r4, r3, r2
0x74 0xfb 0x03 0x25
# CHECK: uxtab16 r1, r2, r3, ror #8
0x32 0xfa 0x93 0xf1
# IT block begin
# CHECK: ittte eq
0x03 0xbf
# CHECK: moveq r3, #3
0x03 0x23
# CHECK: asreq r1, r0, #5
0x41 0x11
# CHECK: lsleq r1, r0, #28
0x01 0x07
Thumb instructions which have reglist operands at the end and predicate operands before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
2010-04-21 03:01:19 +02:00
# CHECK: stmiane r0!, {r1, r2, r3}
0x0e 0xc0
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# IT block end
Thumb instructions which have reglist operands at the end and predicate operands before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
2010-04-21 03:01:19 +02:00
# CHECK: rsbs r1, r2, #0
0x51 0x42
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