2012-02-17 09:55:11 +01:00
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//===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
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2007-06-06 09:42:06 +02:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 09:42:06 +02:00
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//
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-06-06 09:42:06 +02:00
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//
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2008-02-10 19:45:23 +01:00
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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2007-06-06 09:42:06 +02:00
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//
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-06-06 09:42:06 +02:00
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2012-03-17 19:46:09 +01:00
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#include "MipsRegisterInfo.h"
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2007-06-06 09:42:06 +02:00
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#include "Mips.h"
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2012-01-25 04:55:10 +01:00
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#include "MipsAnalyzeImmediate.h"
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2012-06-14 03:17:36 +02:00
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#include "MipsInstrInfo.h"
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2007-07-12 01:21:31 +02:00
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#include "MipsMachineFunction.h"
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2012-12-03 17:50:05 +01:00
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#include "MipsSubtarget.h"
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2015-01-30 00:27:36 +01:00
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#include "MipsTargetMachine.h"
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2012-12-03 17:50:05 +01:00
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2015-06-02 15:14:46 +02:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2012-12-03 17:50:05 +01:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2013-01-02 12:36:10 +01:00
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#include "llvm/IR/Constants.h"
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2014-03-06 01:46:21 +01:00
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#include "llvm/IR/DebugInfo.h"
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2013-12-10 15:29:38 +01:00
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#include "llvm/IR/Function.h"
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2013-01-02 12:36:10 +01:00
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#include "llvm/IR/Type.h"
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2007-06-06 09:42:06 +02:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2009-07-11 22:10:48 +02:00
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#include "llvm/Support/ErrorHandling.h"
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2009-07-25 02:23:56 +02:00
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#include "llvm/Support/raw_ostream.h"
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2012-12-03 17:50:05 +01:00
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2011-06-27 20:32:37 +02:00
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2014-04-22 04:03:14 +02:00
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using namespace llvm;
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2014-04-22 04:41:26 +02:00
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#define DEBUG_TYPE "mips-reg-info"
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2011-06-27 20:32:37 +02:00
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#define GET_REGINFO_TARGET_DESC
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2011-06-24 03:44:41 +02:00
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#include "MipsGenRegisterInfo.inc"
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2007-06-06 09:42:06 +02:00
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2015-03-12 06:43:57 +01:00
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MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
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2007-06-06 09:42:06 +02:00
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2009-08-13 00:10:57 +02:00
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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2008-07-14 16:42:54 +02:00
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2013-08-20 23:08:22 +02:00
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const TargetRegisterClass *
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MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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2015-04-17 11:50:21 +02:00
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MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
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return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
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2013-08-20 23:08:22 +02:00
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}
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2013-01-22 22:34:25 +01:00
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unsigned
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MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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switch (RC->getID()) {
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default:
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return 0;
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2013-08-07 01:08:38 +02:00
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case Mips::GPR32RegClassID:
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case Mips::GPR64RegClassID:
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2013-08-14 02:53:38 +02:00
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case Mips::DSPRRegClassID: {
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2015-03-12 06:43:57 +01:00
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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2013-01-22 22:34:25 +01:00
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return 28 - TFI->hasFP(MF);
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}
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case Mips::FGR32RegClassID:
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return 32;
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case Mips::AFGR64RegClassID:
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return 16;
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case Mips::FGR64RegClassID:
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return 32;
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}
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}
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2011-03-04 18:51:39 +01:00
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// Callee Saved Registers methods
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2011-04-15 23:51:11 +02:00
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//===----------------------------------------------------------------------===//
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2007-08-28 07:13:42 +02:00
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2007-06-06 09:42:06 +02:00
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/// Mips Callee Saved Registers
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2014-04-04 07:16:06 +02:00
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const MCPhysReg *
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MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2015-03-12 06:43:57 +01:00
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const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>();
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2015-10-26 13:38:43 +01:00
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const Function *F = MF->getFunction();
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if (F->hasFnAttribute("interrupt")) {
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if (Subtarget.hasMips64())
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return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList
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: CSR_Interrupt_64_SaveList;
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else
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return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList
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: CSR_Interrupt_32_SaveList;
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}
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2012-03-01 23:27:29 +01:00
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if (Subtarget.isSingleFloat())
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return CSR_SingleFloatOnly_SaveList;
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2013-08-21 01:38:40 +02:00
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if (Subtarget.isABI_N64())
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return CSR_N64_SaveList;
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if (Subtarget.isABI_N32())
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2012-03-01 23:27:29 +01:00
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return CSR_N32_SaveList;
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2012-03-27 22:35:51 +02:00
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2013-08-21 01:38:40 +02:00
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if (Subtarget.isFP64bit())
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return CSR_O32_FP64_SaveList;
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2014-07-10 17:36:12 +02:00
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if (Subtarget.isFPXX())
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return CSR_O32_FPXX_SaveList;
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2013-08-21 01:38:40 +02:00
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return CSR_O32_SaveList;
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2012-03-01 23:27:29 +01:00
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}
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2011-09-23 20:11:56 +02:00
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2015-03-11 23:42:13 +01:00
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const uint32_t *
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MipsRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const {
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2015-03-12 06:43:57 +01:00
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const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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2008-08-06 08:14:43 +02:00
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if (Subtarget.isSingleFloat())
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2012-03-01 23:27:29 +01:00
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return CSR_SingleFloatOnly_RegMask;
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2013-08-21 01:38:40 +02:00
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if (Subtarget.isABI_N64())
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return CSR_N64_RegMask;
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if (Subtarget.isABI_N32())
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2012-03-01 23:27:29 +01:00
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return CSR_N32_RegMask;
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2012-02-28 08:46:26 +01:00
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2013-08-21 01:38:40 +02:00
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if (Subtarget.isFP64bit())
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return CSR_O32_FP64_RegMask;
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2014-07-10 17:36:12 +02:00
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if (Subtarget.isFPXX())
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return CSR_O32_FPXX_RegMask;
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2013-08-21 01:38:40 +02:00
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return CSR_O32_RegMask;
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2007-06-06 09:42:06 +02:00
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}
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Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
llvm-svn: 181641
2013-05-11 00:25:39 +02:00
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const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
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return CSR_Mips16RetHelper_RegMask;
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}
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2007-06-06 09:42:06 +02:00
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BitVector MipsRegisterInfo::
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2010-11-18 22:19:35 +01:00
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getReservedRegs(const MachineFunction &MF) const {
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2014-04-04 07:16:06 +02:00
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static const MCPhysReg ReservedGPR32[] = {
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2012-11-03 01:05:43 +01:00
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Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
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2011-09-23 20:11:56 +02:00
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};
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2014-04-04 07:16:06 +02:00
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static const MCPhysReg ReservedGPR64[] = {
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2012-11-03 01:05:43 +01:00
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Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
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2011-09-23 20:11:56 +02:00
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};
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2007-06-06 09:42:06 +02:00
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BitVector Reserved(getNumRegs());
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2015-03-12 06:43:57 +01:00
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const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
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2012-04-20 09:30:17 +02:00
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typedef TargetRegisterClass::const_iterator RegIter;
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2011-09-23 20:11:56 +02:00
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2013-08-07 01:08:38 +02:00
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for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
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Reserved.set(ReservedGPR32[I]);
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2011-09-23 20:11:56 +02:00
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2014-02-07 18:16:40 +01:00
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// Reserve registers for the NaCl sandbox.
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if (Subtarget.isTargetNaCl()) {
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Reserved.set(Mips::T6); // Reserved for control flow mask.
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Reserved.set(Mips::T7); // Reserved for memory access mask.
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Reserved.set(Mips::T8); // Reserved for thread pointer.
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}
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2013-08-07 01:08:38 +02:00
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for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
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Reserved.set(ReservedGPR64[I]);
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2009-03-21 01:05:07 +01:00
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2014-08-08 12:01:29 +02:00
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// For mno-abicalls, GP is a program invariant!
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if (!Subtarget.isABICalls()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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2013-08-21 01:38:40 +02:00
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if (Subtarget.isFP64bit()) {
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2011-09-23 20:11:56 +02:00
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// Reserve all registers in AFGR64.
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2012-04-20 09:30:17 +02:00
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for (RegIter Reg = Mips::AFGR64RegClass.begin(),
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EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
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2011-09-23 20:11:56 +02:00
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Reserved.set(*Reg);
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2012-04-20 09:30:17 +02:00
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} else {
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2012-11-03 00:36:01 +01:00
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// Reserve all registers in FGR64.
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2012-04-20 09:30:17 +02:00
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for (RegIter Reg = Mips::FGR64RegClass.begin(),
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EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg)
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2011-09-23 20:11:56 +02:00
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Reserved.set(*Reg);
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}
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2012-05-11 03:45:15 +02:00
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// Reserve FP if this function should have a dedicated frame pointer register.
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2015-01-30 00:27:36 +01:00
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if (Subtarget.getFrameLowering()->hasFP(MF)) {
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2012-10-28 07:02:37 +01:00
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if (Subtarget.inMips16Mode())
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Reserved.set(Mips::S0);
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else {
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Reserved.set(Mips::FP);
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Reserved.set(Mips::FP_64);
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2015-06-02 15:14:46 +02:00
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// Reserve the base register if we need to both realign the stack and
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// allocate variable-sized objects at runtime. This should test the
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// same conditions as MipsFrameLowering::hasBP().
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if (needsStackRealignment(MF) &&
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MF.getFrameInfo()->hasVarSizedObjects()) {
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Reserved.set(Mips::S7);
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Reserved.set(Mips::S7_64);
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}
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2012-10-28 07:02:37 +01:00
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}
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2012-05-09 03:38:13 +02:00
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}
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2012-03-27 02:40:56 +02:00
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// Reserve hardware registers.
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Reserved.set(Mips::HWR29);
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2012-09-22 01:48:37 +02:00
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// Reserve DSP control register.
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2013-05-03 20:37:49 +02:00
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Reserved.set(Mips::DSPPos);
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Reserved.set(Mips::DSPSCount);
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Reserved.set(Mips::DSPCarry);
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Reserved.set(Mips::DSPEFI);
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Reserved.set(Mips::DSPOutFlag);
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2012-09-22 01:48:37 +02:00
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2013-08-28 12:26:24 +02:00
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// Reserve MSA control registers.
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Reserved.set(Mips::MSAIR);
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Reserved.set(Mips::MSACSR);
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Reserved.set(Mips::MSAAccess);
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Reserved.set(Mips::MSASave);
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Reserved.set(Mips::MSAModify);
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Reserved.set(Mips::MSARequest);
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Reserved.set(Mips::MSAMap);
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Reserved.set(Mips::MSAUnmap);
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2012-07-10 02:19:06 +02:00
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// Reserve RA if in mips16 mode.
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if (Subtarget.inMips16Mode()) {
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2014-02-14 20:16:39 +01:00
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const MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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2012-07-10 02:19:06 +02:00
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Reserved.set(Mips::RA);
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Reserved.set(Mips::RA_64);
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2013-08-04 03:13:25 +02:00
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Reserved.set(Mips::T0);
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Reserved.set(Mips::T1);
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2014-02-14 20:16:39 +01:00
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if (MF.getFunction()->hasFnAttribute("saveS2") || MipsFI->hasSaveS2())
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2013-12-10 15:29:38 +01:00
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Reserved.set(Mips::S2);
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2012-07-10 02:19:06 +02:00
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}
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2012-08-22 05:18:13 +02:00
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// Reserve GP if small section is used.
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if (Subtarget.useSmallSection()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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2014-07-10 15:38:23 +02:00
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if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
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for (const auto &Reg : Mips::OddSPRegClass)
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Reserved.set(Reg);
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}
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2007-06-06 09:42:06 +02:00
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return Reserved;
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}
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2012-03-28 02:24:17 +02:00
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bool
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MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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2012-04-23 23:39:35 +02:00
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bool
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MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return true;
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}
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2007-06-06 09:42:06 +02:00
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
|
|
|
|
// direct reference.
|
2010-08-27 01:32:16 +02:00
|
|
|
void MipsRegisterInfo::
|
2009-10-07 19:12:56 +02:00
|
|
|
eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
2013-01-31 21:02:54 +01:00
|
|
|
unsigned FIOperandNum, RegScavenger *RS) const {
|
2007-11-05 04:02:32 +01:00
|
|
|
MachineInstr &MI = *II;
|
2007-06-06 09:42:06 +02:00
|
|
|
MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
|
|
2012-08-22 08:07:19 +02:00
|
|
|
DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
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2009-08-23 08:49:22 +02:00
|
|
|
errs() << "<--------->\n" << MI);
|
2008-08-02 21:42:36 +02:00
|
|
|
|
2013-01-31 21:02:54 +01:00
|
|
|
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
2012-01-25 04:55:10 +01:00
|
|
|
uint64_t stackSize = MF.getFrameInfo()->getStackSize();
|
|
|
|
int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2009-08-23 08:49:22 +02:00
|
|
|
DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
|
|
|
|
<< "spOffset : " << spOffset << "\n"
|
|
|
|
<< "stackSize : " << stackSize << "\n");
|
2007-06-06 09:42:06 +02:00
|
|
|
|
2013-01-31 21:02:54 +01:00
|
|
|
eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
|
2007-06-06 09:42:06 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned MipsRegisterInfo::
|
2009-11-12 21:49:22 +01:00
|
|
|
getFrameRegister(const MachineFunction &MF) const {
|
2015-03-12 06:43:57 +01:00
|
|
|
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
|
2015-01-30 00:27:36 +01:00
|
|
|
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
|
|
|
|
bool IsN64 =
|
|
|
|
static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
|
2010-11-18 22:19:35 +01:00
|
|
|
|
2012-10-28 07:02:37 +01:00
|
|
|
if (Subtarget.inMips16Mode())
|
|
|
|
return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
|
|
|
|
else
|
|
|
|
return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
|
|
|
|
(IsN64 ? Mips::SP_64 : Mips::SP);
|
2015-06-02 15:14:46 +02:00
|
|
|
}
|
2012-10-28 07:02:37 +01:00
|
|
|
|
2015-06-02 15:14:46 +02:00
|
|
|
bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
|
Targets: commonize some stack realignment code
This patch does the following:
* Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`.
* Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute.
Multiple targets duplicated the same `needsStackRealignment` code:
- Aarch64.
- ARM.
- Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has.
- PowerPC.
- WebAssembly.
- x86 almost: has an extra `-force-align-stack` option, which the default implementation now has.
The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects:
- AMDGPU
- BPF
- CppBackend
- MSP430
- NVPTX
- Sparc
- SystemZ
- XCore
- Out-of-tree targets
This is a breaking change! `make check` passes.
The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation.
`needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone.
Reviewers: sunfish
Subscribers: aemerson, llvm-commits, jfb
Differential Revision: http://reviews.llvm.org/D11160
llvm-svn: 242727
2015-07-21 00:51:32 +02:00
|
|
|
// Avoid realigning functions that explicitly do not want to be realigned.
|
|
|
|
// Normally, we should report an error when a function should be dynamically
|
|
|
|
// realigned but also has the attribute no-realign-stack. Unfortunately,
|
|
|
|
// with this attribute, MachineFrameInfo clamps each new object's alignment
|
|
|
|
// to that of the stack's alignment as specified by the ABI. As a result,
|
|
|
|
// the information of whether we have objects with larger alignment
|
|
|
|
// requirement than the stack's alignment is already lost at this point.
|
|
|
|
if (!TargetRegisterInfo::canRealignStack(MF))
|
|
|
|
return false;
|
|
|
|
|
2015-06-02 15:14:46 +02:00
|
|
|
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
|
|
|
|
unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64;
|
|
|
|
unsigned BP = Subtarget.isGP32bit() ? Mips::S7 : Mips::S7_64;
|
|
|
|
|
|
|
|
// Support dynamic stack realignment only for targets with standard encoding.
|
|
|
|
if (!Subtarget.hasStandardEncoding())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// We can't perform dynamic stack realignment if we can't reserve the
|
|
|
|
// frame pointer register.
|
|
|
|
if (!MF.getRegInfo().canReserveReg(FP))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// We can realign the stack if we know the maximum call frame size and we
|
|
|
|
// don't have variable sized objects.
|
|
|
|
if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
// We have to reserve the base pointer register in the presence of variable
|
|
|
|
// sized objects.
|
|
|
|
return MF.getRegInfo().canReserveReg(BP);
|
2007-06-06 09:42:06 +02:00
|
|
|
}
|