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llvm-mirror/test/CodeGen/ARM/indirectbr.ll

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Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 05:55:05 +02:00
; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB
Attempt again to fix buildbot failures: make expected output less specific and compile with -mtriple to specify *-apple-darwin targets. llvm-svn: 86081
2009-11-05 01:30:35 +01:00
; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2
[ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode. IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
2013-09-09 16:21:49 +02:00
; RUN: llc < %s -relocation-model=static -mtriple=thumbv8-apple-darwin | FileCheck %s -check-prefix=THUMB2
Add test for ARM indirectbr codegen. llvm-svn: 86042
2009-11-04 20:25:34 +01:00
@nextaddr = global i8* null ; <i8**> [#uses=2]
@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 17:18:27 +02:00
define internal i32 @foo(i32 %i) nounwind {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 08:24:09 +02:00
; ARM-LABEL: foo:
; THUMB-LABEL: foo:
; THUMB2-LABEL: foo:
Add test for ARM indirectbr codegen. llvm-svn: 86042
2009-11-04 20:25:34 +01:00
entry:
%0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
Run the pre-register allocation tail duplication pass by default. Remove the -pre-regalloc-taildup command-line option, and add a new -disable-early-taildup option. llvm-svn: 93597
2010-01-16 01:29:50 +01:00
; indirect branch gets duplicated here
; ARM: bx
Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 00:14:03 +02:00
; THUMB: mov pc,
; THUMB2: mov pc,
Add test for ARM indirectbr codegen. llvm-svn: 86042
2009-11-04 20:25:34 +01:00
br i1 %1, label %bb3, label %bb2
bb2: ; preds = %entry, %bb3
%gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
; ARM: bx
Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 00:14:03 +02:00
; THUMB: mov pc,
Add test for ARM indirectbr codegen. llvm-svn: 86042
2009-11-04 20:25:34 +01:00
indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
bb3: ; preds = %entry
%2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
%gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1]
br label %bb2
L5: ; preds = %bb2
br label %L4
L4: ; preds = %L5, %bb2
%res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ] ; <i32> [#uses=1]
br label %L3
L3: ; preds = %L4, %bb2
%res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ] ; <i32> [#uses=1]
br label %L2
L2: ; preds = %L3, %bb2
Weekly fix of register allocation dependent unit tests. llvm-svn: 130567
2011-04-30 03:37:52 +02:00
; THUMB: muls
Add test for ARM indirectbr codegen. llvm-svn: 86042
2009-11-04 20:25:34 +01:00
%res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1]
%phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1]
br label %L1
L1: ; preds = %L2, %bb2
%res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1]
[ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode. IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
2013-09-09 16:21:49 +02:00
; ARM-LABEL: %L1
Weekly fix of register allocation dependent unit tests. llvm-svn: 130567
2011-04-30 03:37:52 +02:00
; ARM: ldr [[R1:r[0-9]+]], LCPI
; ARM: add [[R1b:r[0-9]+]], pc, [[R1]]
; ARM: str [[R1b]]
[ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode. IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
2013-09-09 16:21:49 +02:00
; THUMB-LABEL: %L1
This adds range checking for "ldr Rn, [pc, #imm]" Thumb instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
2013-07-22 17:49:36 +02:00
; THUMB: ldr
Weekly fix of register allocation dependent unit tests. llvm-svn: 130567
2011-04-30 03:37:52 +02:00
; THUMB: add
This adds range checking for "ldr Rn, [pc, #imm]" Thumb instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
2013-07-22 17:49:36 +02:00
; THUMB: ldr [[R2:r[0-9]+]], LCPI
Weekly fix of register allocation dependent unit tests. llvm-svn: 130567
2011-04-30 03:37:52 +02:00
; THUMB: add [[R2]], pc
; THUMB: str [[R2]]
[ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode. IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
2013-09-09 16:21:49 +02:00
; THUMB2-LABEL: %L1
This adds range checking for "ldr Rn, [pc, #imm]" Thumb instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
2013-07-22 17:49:36 +02:00
; THUMB2: ldr [[R2:r[0-9]+]], LCPI
Weekly fix of register allocation dependent unit tests. llvm-svn: 130567
2011-04-30 03:37:52 +02:00
; THUMB2-NEXT: str{{(.w)?}} [[R2]]
Add test for ARM indirectbr codegen. llvm-svn: 86042
2009-11-04 20:25:34 +01:00
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3
}
fix AsmPrinter::GetBlockAddressSymbol to always return a unique label instead of trying to form one based on the BB name (which causes collisions if the name is empty). This fixes PR6608 llvm-svn: 98495
2010-03-14 18:53:23 +01:00
; ARM: .long Ltmp0-(LPC{{.*}}+8)
; THUMB: .long Ltmp0-(LPC{{.*}}+4)
; THUMB2: .long Ltmp0
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