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llvm-mirror/test/MC/Disassembler/ARM/arm-tests.txt

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Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. llvm-svn: 139250
2011-09-07 21:42:28 +02:00
# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mattr +mp | FileCheck %s
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
2011-07-11 18:48:36 +02:00
# CHECK: addpl r4, pc, #318767104
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
2011-03-24 21:42:48 +01:00
0x4c 0x45 0x8f 0x52
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: b #0
There were two issues fixed: 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707
2011-03-15 23:27:33 +01:00
0x00 0x00 0x00 0xea
# CHECK: bl #7732
0x8d 0x07 0x00 0xeb
# CHECK: bleq #-4
0xff 0xff 0xff 0x0b
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: bfc r8, #0, #16
0x1f 0x80 0xcf 0xe7
# CHECK: bfi r8, r0, #16, #1
0x10 0x88 0xd0 0xe7
PR9030: Fix disassembly of ARM "mov pc, lr" instruction. Patch by Jyun-Yan You. llvm-svn: 124492
2011-01-28 18:50:30 +01:00
# CHECK: mov pc, lr
0x0e 0xf0 0xa0 0xe1
Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
2011-07-11 18:48:36 +02:00
# CHECK: mov pc, #3221225535
MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. Add tests for that. llvm-svn: 129137
2011-04-08 19:29:58 +02:00
0xff 0xf1 0xa0 0xe3
# CHECK: movw r7, #4096
0x00 0x70 0x01 0xe3
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: cmn r0, #1
0x01 0x00 0x70 0xe3
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. Added two test cases to arm-tests.txt. llvm-svn: 110880
2010-08-12 01:35:12 +02:00
# CHECK: dmb
0x5f 0xf0 0x7f 0xf5
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: dmb nshst
0x56 0xf0 0x7f 0xf5
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. Added two test cases to arm-tests.txt. llvm-svn: 110880
2010-08-12 01:35:12 +02:00
# CHECK: dsb
0x4f 0xf0 0x7f 0xf5
Cleaned up the for-disassembly-only entries in the arm instruction table so that the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
2010-08-12 22:46:17 +02:00
# CHECK: dsb st
0x4e 0xf0 0x7f 0xf5
# CHECK: isb
0x6f 0xf0 0x7f 0xf5
ARM refactoring assembly parsing of memory address operands. Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
2011-08-04 01:50:40 +02:00
# FIXME: LDC encoding information is incorrect. Re-enable this along with more
# robust testing for other values when we get it fleshed out and working
# properly.
# CHECKx: ldclvc p5, cr15, [r8], #-0
#0x00 0xf5 0x78 0x7c
Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed to the UAL syntax of LDCL<c>, instead. Add a test case for this change which also tests the removal of assert() from printAddrMode2OffsetOperand(). llvm-svn: 101527
2010-04-16 21:33:23 +02:00
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: ldr r0, [r2], #15
0x0f 0x00 0x92 0xe4
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction as invalid. llvm-svn: 128734
2011-04-01 22:21:38 +02:00
# CHECK: ldr r5, [r7, -r10, lsl #2]
0x0a 0x51 0x17 0xe7
In the same spirit of r101524, which removed the assert() from printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. llvm-svn: 101529
2010-04-16 21:57:21 +02:00
# CHECK: ldrh r0, [r2], #0
0xb0 0x00 0xd2 0xe0
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
# CHECK: ldrh r0, [r2]
0xb0 0x00 0xd2 0xe1
Added another test case for am3offset operand, testing Rn, #+/-imm8. Previous checkin tested Rn, #+/-Rm. llvm-svn: 101418
2010-04-16 01:23:40 +02:00
# CHECK: ldrht r0, [r2], #15
0xbf 0x00 0xf2 0xe0
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not am2offset. Modified the instruction table entry and added a new test case. llvm-svn: 101415
2010-04-16 01:12:47 +02:00
# CHECK: ldrsbtvs lr, [r2], -r9
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
0xd9 0xe0 0x32 0x60
Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not am2offset. Modified the instruction table entry and added a new test case. llvm-svn: 101415
2010-04-16 01:12:47 +02:00
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: lsls r0, r2, #31
0x82 0x0f 0xb0 0xe1
As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends. llvm-svn: 123407
2011-01-13 23:38:16 +01:00
# CHECK: mcr2 p0, #0, r2, c1, c0, #7
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
0xf0 0x20 0x01 0xfe
# CHECK: movt r8, #65535
0xff 0x8f 0x4f 0xe3
Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
2011-07-11 18:48:36 +02:00
# CHECK: mvnspl r7, #1073741885
Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after calling ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2. Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V). [12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done (gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble (gdb) r Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble Reading symbols for shared libraries ++. done 0xf5 0x71 0xf0 0x53 Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1| ------------------------------------------------------------------------------------------------- mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229. Program received signal SIGABRT, Aborted. 0x00007fff88c65886 in __kill () (gdb) bt #0 0x00007fff88c65886 in __kill () #1 0x00007fff88d05eae in abort () #2 0x00007fff88cf2ef0 in __assert_rtn () #3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229 #4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254 #5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236 #6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182 #7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65 #8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153 #9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347 #10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374 (gdb) q The program is running. Exit anyway? (y or n) y [13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ llvm-svn: 101053
2010-04-12 20:46:53 +02:00
0xf5 0x71 0xf0 0x53
ARM "rrx" shift operands do not have an immediate. PR7790. llvm-svn: 110292
2010-08-05 02:34:42 +02:00
# CHECK-NOT: orr r7, r8, r7, rrx #0
# CHECK: orr r7, r8, r7, rrx
0x67 0x70 0x88 0xe1
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: pkhbt r8, r9, r10, lsl #4
0x1a 0x82 0x89 0xe6
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
2011-04-06 01:28:00 +02:00
# CHECK-NOT: pkhbtls r10, r11, r11, lsl #0
# CHECK: pkhbtls r10, r11, r11
0x1b 0xa0 0x8b 0x96
# CHECK: pkhtbmi lr, r1, r6, asr #21
0xd6 0xea 0x81 0x46
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
2010-08-17 19:23:19 +02:00
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: pop {r0, r2, r4, r6, r8, r10}
0x55 0x05 0xbd 0xe8
# CHECK: push {r0, r2, r4, r6, r8, r10}
0x55 0x05 0x2d 0xe9
# CHECK: qsax r8, r9, r10
0x5a 0x8f 0x29 0xe6
# CHECK: rfedb r0!
0x00 0x0a 0x30 0xf9
ARM SRS instruction parsing, diassembly and encoding support. Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
2011-07-29 22:26:09 +02:00
# CHECK: srsdb sp!, #19
0x13 0x05 0x6d 0xf9
# CHECK: srsia sp, #9
0x09 0x05 0xcd 0xf8
Add an ARM RSBrr instruction for disassembly only. Partial fix for PR7792. llvm-svn: 110358
2010-08-05 20:23:43 +02:00
# CHECK-NOT: rsbeq r0, r2, r0, lsl #0
# CHECK: rsbeq r0, r2, r0
0x00 0x00 0x62 0x00
ARM instructions that are both predicated and set the condition codes have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! llvm-svn: 116563
2010-10-15 05:23:44 +02:00
# CHECK-NOT: rscseq r0, r0, r1, lsl #0
# CHECK: rscseq r0, r0, r1
Add an ARM RSCrr instruction for disassembly only. Partial fix for PR7792. llvm-svn: 110361
2010-08-05 20:59:36 +02:00
0x01 0x00 0xf0 0x00
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: sbcs r0, pc, #1
0x01 0x00 0xdf 0xe2
# CHECK: sbfx r0, r1, #0, #8
0x51 0x00 0xa7 0xe7
# CHECK: ssat r8, #1, r10, lsl #8
0x1a 0x84 0xa0 0xe6
Move the ARM SSAT and USAT optional shift amount operand out of the instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
2010-08-12 01:10:46 +02:00
# CHECK-NOT: ssatmi r0, #17, r12, lsl #0
# CHECK: ssatmi r0, #17, r12
0x1c 0x00 0xb0 0x46
Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
2010-04-03 00:27:38 +02:00
# CHECK: stmdb r10!, {r4, r5, r6, r7, lr}
0xf0 0x40 0x2a 0xe9
# CHECK: teq r0, #31
0x1f 0x00 0x30 0xe3
# CHECK: ubfx r0, r0, #16, #1
0x50 0x08 0xe0 0xe7
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. llvm-svn: 110894
2010-08-12 03:40:54 +02:00
# CHECK: usat r8, #0, r10, asr #32
0x5a 0x80 0xe0 0xe6
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
2010-10-13 23:00:04 +02:00
# CHECK: setend be
0x00 0x02 0x01 0xf1
# CHECK: setend le
0x00 0x00 0x01 0xf1
Fix encoding and add parsing support for the arm/thumb CPS instruction: - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
2011-02-14 14:09:44 +01:00
# CHECK: cpsie aif
0xc0 0x01 0x08 0xf1
# CHECK: cps #15
0x0f 0x00 0x02 0xf1
# CHECK: cpsie if, #10
0xca 0x00 0x0a 0xf1
Add assembly parsing support for "msr" and also fix its encoding. Also add testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
2011-02-18 20:45:59 +01:00
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. llvm-svn: 142626
2011-10-21 00:23:58 +02:00
# CHECK: msr CPSR_fc, r0
0x00 0xf0 0x29 0xe1
# CHECK: msrmi CPSR_c, #4043309056
0xf1 0xf4 0x21 0x43
Fixes an assertion failure while disassembling ARM rsbs reg/reg form. Patch by Ted Kremenek! llvm-svn: 126895
2011-03-03 00:08:33 +01:00
# CHECK: rsbs r6, r7, r8
0x08 0x60 0x77 0xe0
pr9367: Add missing predicated BLX instructions. Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
2011-03-03 02:41:01 +01:00
# CHECK: blxeq r5
0x35 0xff 0x2f 0x01
TableGen should not ignore BX instructions for the ARM disassembler. pr9368. llvm-svn: 126931
2011-03-03 08:19:52 +01:00
# CHECK: bx r12
0x1c 0xff 0x2f 0xe1
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan llvm-svn: 127354
2011-03-09 21:01:14 +01:00
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
2011-05-22 19:51:04 +02:00
# CHECK: bxeq r5
0x15 0xff 0x2f 0x01
LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan llvm-svn: 127354
2011-03-09 21:01:14 +01:00
# CHECK: uqadd16mi r6, r11, r8
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
0x18 0x6F 0x6b 0x46
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
2011-03-15 02:13:17 +01:00
# CHECK: str r0, [sp, #4]
0x04 0x00 0x8d 0xe5
# CHECK: str r1, [sp]
0x00 0x10 0x8d 0xe5
# CHECK: ldr r3, [pc, #144]
0x90 0x30 0x9f 0xe5
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
2011-04-01 20:26:38 +02:00
# CHECK: ldr r3, [r0, #-4]
0x4 0x30 0x10 0xe5
# CHECK: ldr r5, [sp, r0, lsl #1]!
0x80 0x50 0xbd 0xe7
# CHECK: ldr r5, [r7], -r0, lsr #2
0x20 0x51 0x17 0xe6
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
2011-03-15 02:13:17 +01:00
# CHECK: strdeq r2, r3, [r0], -r8
0xf8 0x24 0x00 0x00
Fixed an assert by the ARM disassembler for LDRD_PRE/POST. The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. llvm-svn: 127935
2011-03-19 02:16:20 +01:00
LDRD now prints out two dst registers. llvm-svn: 128909
2011-04-05 20:53:14 +02:00
# CHECK: ldrdeq r2, r3, [r0], -r12
Fixed an assert by the ARM disassembler for LDRD_PRE/POST. The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. llvm-svn: 127935
2011-03-19 02:16:20 +01:00
0xdc 0x24 0x00 0x00
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). We now tag them as IndexModePost. This fixed http://llvm.org/bugs/show_bug.cgi?id=9530. llvm-svn: 128113
2011-03-22 23:28:49 +01:00
# CHECK: ldrbt r3, [r4], -r5, lsl #12
0x05 0x36 0x74 0xe6
Add disassembly test cases for: A8.6.292 VCMPE llvm-svn: 128120
2011-03-23 00:08:56 +01:00
# CHECK: vcmpe.f64 d8, #0
0xc0 0x8b 0xb5 0xee
The r128103 fix to cope with the removal of addressing modes from the MC instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
2011-03-24 01:28:38 +01:00
Add and modify some tests. llvm-svn: 128476
2011-03-29 21:08:52 +02:00
# CHECK: vldmdb r2!, {s7, s8, s9, s10, s11}
0x05 0x3a 0x72 0xed
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
2011-11-15 00:03:21 +01:00
# CHECK: vldr s23, [r2, #660]
Add and modify some tests. llvm-svn: 128476
2011-03-29 21:08:52 +02:00
0xa5 0xba 0xd2 0xed
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821). We now tag them as IndexModePost. llvm-svn: 128189
2011-03-24 02:07:26 +01:00
# CHECK: strtvc r5, [r3], r0, lsr #20
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
2011-04-06 03:18:32 +02:00
0x20 0x5a 0xa3 0x76
Load/Store Multiple: These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191
2011-03-24 02:40:42 +01:00
# CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x8d 0x39
# CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc}
0x11 0x99 0x1d 0xe9
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that. rdar://problem/9184053 llvm-svn: 128285
2011-03-25 18:31:16 +01:00
# CHECK: swpge r3, r2, [r6]
0x92 0x30 0x06 0xa1
Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt. llvm-svn: 128306
2011-03-26 00:02:58 +01:00
# CHECK: umull r1, r2, r3, r4
0x93 0x14 0x82 0xe0
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
2011-03-28 20:41:58 +02:00
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
2011-08-09 22:55:18 +02:00
# CHECK: pldw [pc, #-0]
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
2011-03-28 20:41:58 +02:00
0x00 0xf0 0x1f 0xf5
# CHECK: pli [pc, #-0]
0x00 0xf0 0x5f 0xf4
# CHECK: pli [r3, r1, lsl #2]
0x01 0xf1 0xd3 0xf6
A8.6.188 STC, STC2 The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
2011-03-29 21:49:38 +02:00
Update test for r141704. llvm-svn: 141705
2011-10-11 22:18:50 +02:00
# CHECK: stc p2, c4, [r9], {157}
A8.6.188 STC, STC2 The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
2011-03-29 21:49:38 +02:00
0x9d 0x42 0x89 0xec
Update test for r141704. llvm-svn: 141705
2011-10-11 22:18:50 +02:00
# CHECK: stc2 p2, c4, [r9], {157}
A8.6.188 STC, STC2 The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
2011-03-29 21:49:38 +02:00
0x9d 0x42 0x89 0xfc
Add BLXi to the instruction table for disassembly purpose. A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
2011-03-31 19:53:50 +02:00
ARM Disassembler: sign extend branch immediates. Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
2011-08-10 00:02:50 +02:00
# CHECK: bne #-24
0xfa 0xff 0xff 0x1a
Add BLXi to the instruction table for disassembly purpose. A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
2011-03-31 19:53:50 +02:00
# CHECK: blx #60
0x0f 0x00 0x00 0xfa
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746
2011-04-02 00:32:51 +02:00
# CHECK-NOT: adcs r10, r8, r0, asr #6
# CHECK: adcshi r10, r8, r0, asr #6
0x40 0xa3 0xb8 0x80
# CHECK: adcshi r10, r8, r0, asr r3
0x50 0xa3 0xb8 0x80
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
2011-04-02 04:24:54 +02:00
# CHECK: streq r1, [sp], #-1567
0x1f 0x16 0xd 0x4
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
2011-04-05 22:32:23 +02:00
# CHECK: mrchs p2, #3, r11, c13, c6, #6
0xd6 0xb2 0x7d 0x2e
Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
2011-04-06 03:18:32 +02:00
# CHECK: smlsldx r4, r12, r11, r4
0x7b 0x44 0x4c 0xe7
Add some more comments about checkings of invalid register numbers. And two test cases. llvm-svn: 129090
2011-04-07 20:33:19 +02:00
# CHECK: lsl r3, r2, r1
0x12 0x31 0xa0 0xe1
Add sanity checking for invalid register encodings for signed/unsigned extend instructions. Add some test cases. llvm-svn: 129098
2011-04-07 21:28:58 +02:00
# CHECK: sxtab r9, r8, r5
0x75 0x90 0xa8 0xe6
# CHECK: sxtb r9, r5, ror #8
0x75 0x94 0xaf 0xe6
Add sanity checking for bad register specifier(s) for the DPFrm instructions. Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
2011-04-08 02:29:09 +02:00
# CHECK: bfc r5, #0, #16
0x1f 0x50 0xcf 0xe7
# CHECK: bfi r5, r6, #0, #16
0x16 0x50 0xcf 0xe7
# CHECK: sbfx r5, r6, #8, #8
0x56 0x54 0xa7 0xe7
# CHECK: rsb pc, r5, r0
0x00 0xf0 0x65 0xe0
# CHECK: uqadd8 r5, r6, r7
0x97 0x5f 0x66 0xe6
# CHECK: uqsax r5, r6, r7
0x57 0x5f 0x66 0xe6
Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. PR9650 rdar://problem/9257565 llvm-svn: 129147
2011-04-08 21:41:22 +02:00
# CHECK: smmlareq r0, r0, r0, r0
0x30 0x00 0x50 0x07
Add tests for A8.6.110 NOP. llvm-svn: 130345
2011-04-28 01:29:21 +02:00
# CHECK: nop
0x00 0xf0 0x20 0xe3
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. llvm-svn: 137322
2011-08-11 20:41:59 +02:00
# CHECK: andeq r0, r0, r0, lsr #32
0x20 0x00 0x00 0x00
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. llvm-svn: 137347
2011-08-11 22:47:56 +02:00
# CHECK: strb r3, [r2], #1
0x01 0x30 0xc2 0xe4
Add testcase for STRH. Patch by James Molloy. llvm-svn: 137644
2011-08-15 22:12:03 +02:00
# CHECK: strheq r0, [r0, -r0]
0xb0 0x00 0x00 0x01
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. llvm-svn: 138000
2011-08-19 00:31:17 +02:00
# CHECK: rfedb #4!
0x14 0x0 0x32 0xf9
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. Found by randomized testing. llvm-svn: 138003
2011-08-19 00:47:44 +02:00
Update test for r141704. llvm-svn: 141705
2011-10-11 22:18:50 +02:00
# CHECK: stc2l p0, c0, [r2], #-96
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. Found by randomized testing. llvm-svn: 138003
2011-08-19 00:47:44 +02:00
0x18 0x0 0x62 0xfc
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. llvm-svn: 143557
2011-11-02 19:03:14 +01:00
# CHECK: ldmgt sp!, {r9}
0x00 0x02 0xbd 0xc8
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